C++ GPIO_PDDR_PDD函数代码示例

int cam_init() {
	//
	// disable interrupt
	//
	disable_irq(64);
	
	//
	// FTM2 configuration
	//
	
	// enable the clock for FTM2
	SIM_SCGC3 |= SIM_SCGC3_FTM2_MASK;
	
	// enable write-able mode for FTM2
	FTM2_MODE |= FTM_MODE_WPDIS_MASK;
	
	// turn off Status and Control
	FTM2_SC = 0;
	
	// makes the initial counter value for FTM2
	FTM2_CNTIN = 0;
	
	// writing any value to CNT loads the counter with CNTIN for FTM 2
	FTM2_CNT = 0;
	
	// CHIE enables interrupts as an ISR (used by ADC function after
	// clock pulses)
	FTM2_C0SC = FTM_CnSC_MSB_MASK | FTM_CnSC_ELSB_MASK | FTM_CnSC_CHIE_MASK;
	
	// when counter == mod, the counter resets, set MOD value
	FTM2_MOD = CAM_MOD_INIT;
	FTM2_C0V = 0;
	
	// set clock prescaler for FTM2
	FTM2_SC |= FTM_SC_PS(2);
	
	// set main clock as BUS clock (50 MHz) for FTM2
	FTM2_SC |= FTM_SC_CLKS(1);	
	
	//
	// GPIO configuration for top level pins
	//
		
	// enable the clock for Port A
	SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
	// set Port A Pin 14 for GPIO functionality (A22)
	PORTA_PCR14 = (0|PORT_PCR_MUX(1));
	// set Port A Pin 14 for output to drive the SI pulse
	GPIOA_PDDR |= GPIO_PDDR_PDD(GPIO_PIN(14));
	
	// set Port A Pin 10 for GPIO functionality (B66)
	PORTA_PCR10 = (0|PORT_PCR_MUX(3));
	// set Port A Pin 10 for output to drive the camera clock
	GPIOA_PDDR |= GPIO_PDDR_PDD(GPIO_PIN(10));

	
	
	return CAM_RET_SUCCESS;
}

/**
* @brief Sets up the GPIOs for fusion signaling
*/
void FusionSignal_Init()
{
    /* Set system clock gating to enable gate to port B */
    SIM->SCGC5 |= SIM_SCGC5_PORTB_MASK;

    /* Set Port B, pin 8 and 9 to GPIO mode */
    PORTB->PCR[8] = PORT_PCR_MUX(1); /* not using |= assignment here due to some of the flags being undefined at reset */
    PORTB->PCR[9] = PORT_PCR_MUX(1);

    /* Data direction for port B, pin 8 and 9  to output */
    GPIOB->PDDR |= GPIO_PDDR_PDD(1 << 8) | GPIO_PDDR_PDD(1 << 9);
}

/*
** ===================================================================
**     Method      :  PTC_Init (component Init_GPIO)
**     Description :
**         This method initializes registers of the GPIO module
**         according to the Peripheral Initialization settings.
**         Call this method in user code to initialize the module. By
**         default, the method is called by PE automatically; see "Call
**         Init method" property of the component for more details.
**     Parameters  : None
**     Returns     : Nothing
** ===================================================================
*/
void PTC_Init(void)
{
  /* GPIOC_PSOR: PTSO|=0x10 */
  GPIOC_PSOR |= GPIO_PSOR_PTSO(0x10);
  /* GPIOC_PCOR: PTCO&=~0x10 */
  GPIOC_PCOR &= (uint32_t)~(uint32_t)(GPIO_PCOR_PTCO(0x10));
  /* GPIOC_PDDR: PDD&=~0x62,PDD|=0x10 */
  GPIOC_PDDR = (uint32_t)((GPIOC_PDDR & (uint32_t)~(uint32_t)(
                GPIO_PDDR_PDD(0x62)
               )) | (uint32_t)(
                GPIO_PDDR_PDD(0x10)
               ));
}

/*---------------------------------------------------------------------------*/
void
leds_arch_init(void)
{
	/**
	 * Initialize blue led 
	*/
	/* Configure pin as output */
    GPIOD_PDDR |= GPIO_PDDR_PDD(0x02);                                   
    /* Set initialization value */
    GPIOD_PDOR &= (uint32_t)~(uint32_t)(GPIO_PDOR_PDO(0x02));                                   
    /* Initialization of Port Control register */
    PORTD_PCR1 = (uint32_t)((PORTD_PCR1 & (uint32_t)~(uint32_t)(
                  PORT_PCR_ISF_MASK |
                  PORT_PCR_MUX(0x06)
                 )) | (uint32_t)(
                  PORT_PCR_MUX(0x01)
                 ));
	
	/**
	 * Initialize green led 
	*/
	/* Configure pin as output */
  	GPIOB_PDDR |= GPIO_PDDR_PDD(0x00080000);                                   
  	/* Set initialization value */
  	GPIOB_PDOR &= (uint32_t)~(uint32_t)(GPIO_PDOR_PDO(0x00080000));                                   
  	/* Initialization of Port Control register */
	PORTB_PCR19 = (uint32_t)((PORTB_PCR19 & (uint32_t)~(uint32_t)(
                 PORT_PCR_ISF_MASK |
                 PORT_PCR_MUX(0x06)
                )) | (uint32_t)(
                 PORT_PCR_MUX(0x01)
                ));
	   
  	/**
  	 * Initialize red led 
  	*/
  	/* Configure pin as output */
	GPIOB_PDDR |= GPIO_PDDR_PDD(0x00040000);                                   
  	/* Set initialization value */
	GPIOB_PDOR &= (uint32_t)~(uint32_t)(GPIO_PDOR_PDO(0x00040000));                                   
  	/* Initialization of Port Control register */
	PORTB_PCR18 = (uint32_t)((PORTB_PCR18 & (uint32_t)~(uint32_t)(
                 PORT_PCR_ISF_MASK |
                 PORT_PCR_MUX(0x06)
                )) | (uint32_t)(
                 PORT_PCR_MUX(0x01)
                ));         
}

/* ===================================================================*/
LDD_TDeviceData* TraccionTrasera_Direccion_Init(LDD_TUserData *UserDataPtr)
{
  /* Allocate device structure */
  TraccionTrasera_Direccion_TDeviceDataPtr DeviceDataPrv;

  /* {FreeRTOS RTOS Adapter} Driver memory allocation: RTOS function call is defined by FreeRTOS RTOS Adapter property */
  DeviceDataPrv = (TraccionTrasera_Direccion_TDeviceData *)pvPortMalloc(sizeof(TraccionTrasera_Direccion_TDeviceData));
  #if FreeRTOS_CHECK_MEMORY_ALLOCATION_ERRORS
  if (DeviceDataPrv == NULL) {
    return (NULL);
  }
  #endif
  DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */
  /* Configure pin as output */
  /* GPIOE_PDDR: PDD|=8 */
  GPIOE_PDDR |= GPIO_PDDR_PDD(0x08);
  /* Set initialization value */
  /* GPIOE_PDOR: PDO&=~8 */
  GPIOE_PDOR &= (uint32_t)~(uint32_t)(GPIO_PDOR_PDO(0x08));
  /* Initialization of Port Control register */
  /* PORTE_PCR3: ISF=0,MUX=1 */
  PORTE_PCR3 = (uint32_t)((PORTE_PCR3 & (uint32_t)~(uint32_t)(
                PORT_PCR_ISF_MASK |
                PORT_PCR_MUX(0x06)
               )) | (uint32_t)(
                PORT_PCR_MUX(0x01)
               ));
  /* Registration of the device structure */
  PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_TraccionTrasera_Direccion_ID,DeviceDataPrv);
  return ((LDD_TDeviceData *)DeviceDataPrv);
}

/* ===================================================================*/
LDD_TDeviceData* BitIoLdd2_Init(LDD_TUserData *UserDataPtr)
{
  /* Allocate device structure */
  BitIoLdd2_TDeviceDataPtr DeviceDataPrv;

  /* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
  DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
  DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */
  /* Configure pin as output */
  /* GPIOB_PDDR: PDD|=0x0200 */
  GPIOB_PDDR |= GPIO_PDDR_PDD(0x0200);
  /* Set initialization value */
  /* GPIOB_PDOR: PDO&=~0x0200 */
  GPIOB_PDOR &= (uint32_t)~(uint32_t)(GPIO_PDOR_PDO(0x0200));
  /* Initialization of Port Control register */
  /* PORTB_PCR9: ISF=0,MUX=1 */
  PORTB_PCR9 = (uint32_t)((PORTB_PCR9 & (uint32_t)~(uint32_t)(
                PORT_PCR_ISF_MASK |
                PORT_PCR_MUX(0x06)
               )) | (uint32_t)(
                PORT_PCR_MUX(0x01)
               ));
  /* Registration of the device structure */
  PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_BitIoLdd2_ID,DeviceDataPrv);
  return ((LDD_TDeviceData *)DeviceDataPrv);
}

/* ===================================================================*/
LDD_TDeviceData* LEDRed_Init(LDD_TUserData *UserDataPtr)
{
  /* Allocate LDD device structure */
  LEDRed_TDeviceData *DeviceDataPrv;

  /* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
  DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
  /* Save RTOS Device structure */
  DeviceDataPrv->UserData = UserDataPtr; /* Store the RTOS device structure */
  /* Enable device clock gate */
  /* SIM_SCGC5: PORTC=1 */
  SIM_SCGC5 |= SIM_SCGC5_PORTC_MASK;
  /* GPIOC_PDOR: PDO|=0x0200 */
  GPIOC_PDOR |= GPIO_PDOR_PDO(0x0200);
  /* GPIOC_PDDR: PDD|=0x0200 */
  GPIOC_PDDR |= GPIO_PDDR_PDD(0x0200);
  /* Initialization of pin routing */
  /* PORTC_PCR9: ISF=0,MUX=1 */
  PORTC_PCR9 = (uint32_t)((PORTC_PCR9 & (uint32_t)~(uint32_t)(
                PORT_PCR_ISF_MASK |
                PORT_PCR_MUX(0x06)
               )) | (uint32_t)(
                PORT_PCR_MUX(0x01)
               ));
  /* Registration of the device structure */
  PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_LEDRed_ID,DeviceDataPrv);
  return ((LDD_TDeviceData *)DeviceDataPrv);
}

/* ===================================================================*/
LDD_TDeviceData* CD1_Init(LDD_TUserData *UserDataPtr)
{
  /* Allocate device structure */
  CD1_TDeviceDataPtr DeviceDataPrv;

  /* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
  DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
  DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */
  /* Enable device clock gate */
  /* SIM_SCGC5: PORTC=1 */
  SIM_SCGC5 |= SIM_SCGC5_PORTC_MASK;
  /* Configure pin as input */
  /* GPIOC_PDDR: PDD&=~0x0100 */
  GPIOC_PDDR &= (uint32_t)~(uint32_t)(GPIO_PDDR_PDD(0x0100));
  /* Initialization of pin routing */
  /* PORTC_PCR8: ISF=0,MUX=1 */
  PORTC_PCR8 = (uint32_t)((PORTC_PCR8 & (uint32_t)~(uint32_t)(
                PORT_PCR_ISF_MASK |
                PORT_PCR_MUX(0x06)
               )) | (uint32_t)(
                PORT_PCR_MUX(0x01)
               ));
  /* Registration of the device structure */
  PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_CD1_ID,DeviceDataPrv);
  return ((LDD_TDeviceData *)DeviceDataPrv);
}

/* ===================================================================*/
LDD_TDeviceData* GPIO2_Init(LDD_TUserData *UserDataPtr)
{
  /* Allocate LDD device structure */
  GPIO2_TDeviceData *DeviceDataPrv;

  /* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
  DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
  /* Save RTOS Device structure */
  DeviceDataPrv->UserData = UserDataPtr; /* Store the RTOS device structure */
  /* GPIOE_PDOR: PDO|=0x000C0000 */
  GPIOE_PDOR |= GPIO_PDOR_PDO(0x000C0000);
  /* GPIOE_PDDR: PDD|=0x000C0000 */
  GPIOE_PDDR |= GPIO_PDDR_PDD(0x000C0000);
  /* Initialization of Port Control registers */
  /* PORTE_PCR18: ISF=0,MUX=1 */
  PORTE_PCR18 = (uint32_t)((PORTE_PCR18 & (uint32_t)~(uint32_t)(
                 PORT_PCR_ISF_MASK |
                 PORT_PCR_MUX(0x06)
                )) | (uint32_t)(
                 PORT_PCR_MUX(0x01)
                ));
  /* PORTE_PCR19: ISF=0,MUX=1 */
  PORTE_PCR19 = (uint32_t)((PORTE_PCR19 & (uint32_t)~(uint32_t)(
                 PORT_PCR_ISF_MASK |
                 PORT_PCR_MUX(0x06)
                )) | (uint32_t)(
                 PORT_PCR_MUX(0x01)
                ));
  /* Registration of the device structure */
  PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_GPIO2_ID,DeviceDataPrv);
  return ((LDD_TDeviceData *)DeviceDataPrv);
}

void display_7segments_initDisplays()
{
	// Gate clock to PORTC
	SIM_SCGC5 |= (SIM_SCGC5_PORTC_MASK);

	// Setting pin muxes to ALT1 (GPIO)
	PORTC_PCR0 = PORT_PCR_MUX(D7S_ALT);
	PORTC_PCR1 = PORT_PCR_MUX(D7S_ALT);
	PORTC_PCR2 = PORT_PCR_MUX(D7S_ALT);
	PORTC_PCR3 = PORT_PCR_MUX(D7S_ALT);
	PORTC_PCR4 = PORT_PCR_MUX(D7S_ALT);
	PORTC_PCR5 = PORT_PCR_MUX(D7S_ALT);
	PORTC_PCR6 = PORT_PCR_MUX(D7S_ALT);
	PORTC_PCR7 = PORT_PCR_MUX(D7S_ALT);

	PORTC_PCR10 = PORT_PCR_MUX(D7S_ALT);
	PORTC_PCR11 = PORT_PCR_MUX(D7S_ALT);
	PORTC_PCR12 = PORT_PCR_MUX(D7S_ALT);
	PORTC_PCR13 = PORT_PCR_MUX(D7S_ALT);

	// Ungating port clock to preserve power if defined
	#ifdef D7S_UNGATE_CLOCK
		SIM_SCGC5 &= ~SIM_SCGC5_PORTC_MASK;
	#endif

	// Setting GPIO direction to output
	GPIOC_PDDR |= GPIO_PDDR_PDD(D7S_DIR);

}

/* ===================================================================*/
LDD_TDeviceData* BitIoLdd4_Init(LDD_TUserData *UserDataPtr)
{
  /* Allocate device structure */
  BitIoLdd4_TDeviceDataPtr DeviceDataPrv;

  /* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
  DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
  DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */
  /* Enable device clock gate */
  /* SIM_SCGC5: PORTD=1 */
  SIM_SCGC5 |= SIM_SCGC5_PORTD_MASK;
  /* Configure pin as output */
  /* GPIOD_PDDR: PDD|=8 */
  GPIOD_PDDR |= GPIO_PDDR_PDD(0x08);
  /* Set initialization value */
  /* GPIOD_PDOR: PDO&=~8 */
  GPIOD_PDOR &= (uint32_t)~(uint32_t)(GPIO_PDOR_PDO(0x08));
  /* Initialization of pin routing */
  /* PORTD_PCR3: ISF=0,MUX=1 */
  PORTD_PCR3 = (uint32_t)((PORTD_PCR3 & (uint32_t)~(uint32_t)(
                PORT_PCR_ISF_MASK |
                PORT_PCR_MUX(0x06)
               )) | (uint32_t)(
                PORT_PCR_MUX(0x01)
               ));
  /* Registration of the device structure */
  PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_BitIoLdd4_ID,DeviceDataPrv);
  return ((LDD_TDeviceData *)DeviceDataPrv);
}

/* ===================================================================*/
void Blue_LED_Deinit(LDD_TDeviceData *DeviceDataPtr)
{
  (void)DeviceDataPtr;                 /* Parameter is not used, suppress unused argument warning */
  /* GPIOD_PDDR: PDD&=~2 */
  GPIOD_PDDR &= (uint32_t)~(uint32_t)(GPIO_PDDR_PDD(0x02));                                   
  /* Unregistration of the device structure */
  PE_LDD_UnregisterDeviceStructure(PE_LDD_COMPONENT_Blue_LED_ID);
  /* Deallocation of the device structure */
  /* {Default RTOS Adapter} Driver memory deallocation: Dynamic allocation is simulated, no deallocation code is generated */
}

/**
 * @brief Sets up the GPIOs for LED driving
 */
void LED_Init()
{
	/* Set system clock gating to enable gate to port B */
	SIM->SCGC5 |= SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTD_MASK;
	
	/* Set Port B, pin 18 and 19 to GPIO mode */
	PORTB->PCR[18] = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK; /* not using |= assignment here due to some of the flags being undefined at reset */
	PORTB->PCR[19] = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK;
	
	/* Set Port d, pin 1 GPIO mode */
	PORTD->PCR[1] = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK;
		
	/* Data direction for port B, pin 18 and 19 and port D, pin 1 set to output */ 
	GPIOB->PDDR |= GPIO_PDDR_PDD(1<<18) | GPIO_PDDR_PDD(1<<19);
	GPIOD->PDDR |= GPIO_PDDR_PDD(1<<1);
	
	/* disable all leds */
	LED_Off();
}

void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
{
unsigned portCHAR ucLED = ( unsigned portCHAR ) ( ( unsigned portBASE_TYPE ) 2 << uxLED );

	if( uxLED < partstNUM_LEDs )
	{
		portENTER_CRITICAL();
		{
                                GPIOA_PDDR^=GPIO_PDDR_PDD(GPIO_PIN(10) | GPIO_PIN(11) | GPIO_PIN(28) | GPIO_PIN(29) );
		}
		portEXIT_CRITICAL();
	}
}

void rt_hw_led_init(void)
{
    SIM->SCGC5 |= (1 << SIM_SCGC5_PORTB_SHIFT);
    SIM->SCGC5 |= (1 << SIM_SCGC5_PORTE_SHIFT);

    PORTB->PCR[21] &= ~PORT_PCR_MUX_MASK;
    PORTB->PCR[21] |= PORT_PCR_MUX(1);   //PTB21 is GPIO pin

    PORTB->PCR[22] &= ~PORT_PCR_MUX_MASK;
    PORTB->PCR[22] |= PORT_PCR_MUX(1);  //PTB22 is GPIO pin

    PORTE->PCR[26] &= ~PORT_PCR_MUX_MASK;
    PORTE->PCR[26] |= PORT_PCR_MUX(1);  //PTE26 is GPIO pin

    /* Switch LEDs off and enable output*/
    PTB->PDDR |= GPIO_PDDR_PDD(led_mask[1] | led_mask[0]);
    PTE->PDDR |= GPIO_PDDR_PDD(led_mask[2]);

    rt_hw_led_off(LED_RED);
    rt_hw_led_off(LED_GREEN);
    rt_hw_led_off(LED_BLUE);
}