本文整理汇总了C++中GPIOPinTypeSSI函数的典型用法代码示例。如果您正苦于以下问题:C++ GPIOPinTypeSSI函数的具体用法?C++ GPIOPinTypeSSI怎么用?C++ GPIOPinTypeSSI使用的例子?那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。
在下文中一共展示了GPIOPinTypeSSI函数的15个代码示例,这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞,您的评价将有助于系统推荐出更棒的C++代码示例。
示例1: Zone_Init
void Zone_Init(void)
{
SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
GPIOPinTypeSSI(GPIO_PORTA_BASE,
GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5);
GPIOPadConfigSet(GPIO_PORTA_BASE,
GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5,
GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD_WPU);
SSIDisable(SSI0_BASE);
SSIConfigSetExpClk(SSI0_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0,
SSI_MODE_MASTER, 2000000, 8);
GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_3);
GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3,
GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD_WPU);
SSIEnable(SSI0_BASE);
while(SSIBusy(SSI0_BASE)) {}
SSIDataPut(SSI0_BASE, ZONE_NONE);
}
示例2: RIT128x96x4Enable
//*****************************************************************************
//
//! Enable the SSI component of the OLED display driver.
//!
//! \param ulFrequency specifies the SSI Clock Frequency to be used.
//!
//! This function initializes the SSI interface to the OLED display.
//!
//! \return None.
//
//*****************************************************************************
void
RIT128x96x4Enable(unsigned long ulFrequency)
{
//
// Disable the SSI port.
//
SSIDisable(SSI0_BASE);
//
// Configure the SSI0 port for master mode.
//
SSIConfigSetExpClk(SSI0_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_3,
SSI_MODE_MASTER, ulFrequency, 8);
//
// (Re)Enable SSI control of the FSS pin.
//
GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_3);
GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA,
GPIO_PIN_TYPE_STD_WPU);
//
// Enable the SSI port.
//
SSIEnable(SSI0_BASE);
//
// Indicate that the RIT driver can use the SSI Port.
//
HWREGBITW(&g_ulSSIFlags, FLAG_SSI_ENABLED) = 1;
}
示例3: main
int main()
{
SysCtlClockSet(SYSCTL_SYSDIV_2_5|SYSCTL_USE_PLL|SYSCTL_XTAL_16MHZ|SYSCTL_OSC_MAIN);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI2);
GPIOPinConfigure(GPIO_PB4_SSI2CLK);
GPIOPinConfigure(GPIO_PB7_SSI2TX);
GPIOPinTypeSSI(GPIO_PORTB_BASE,GPIO_PIN_4|GPIO_PIN_7);
SSIConfigSetExpClk(SSI2_BASE,SysCtlClockGet(),SSI_FRF_MOTO_MODE_0,SSI_MODE_MASTER,2000000,8);
SSIEnable(SSI2_BASE);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
GPIOPinTypeGPIOOutput(GPIO_PORTA_BASE, GPIO_PIN_2|GPIO_PIN_3);
GPIOPinWrite(GPIO_PORTA_BASE,GPIO_PIN_2,0);
GPIOPinWrite(GPIO_PORTA_BASE,GPIO_PIN_3,0);
GPIOPinTypeGPIOOutput(GPIO_PORTB_BASE, GPIO_PIN_6);
GPIOPinWrite(GPIO_PORTB_BASE,GPIO_PIN_6,0);
while(1)
{
SSIDataPut(SSI2_BASE,0xAA);
latch();
SysCtlDelay(SysCtlClockGet()/10);
SSIDataPut(SSI2_BASE,0x55);
latch();
SysCtlDelay(SysCtlClockGet()/10);
}
}
示例4: EK_TM4C123GXL_initWiFi
/*
* ======== EK_TM4C123GXL_initWiFi ========
*/
void EK_TM4C123GXL_initWiFi(void)
{
/* Configure SSI2 */
SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI2);
GPIOPinConfigure(GPIO_PB4_SSI2CLK);
GPIOPinConfigure(GPIO_PB6_SSI2RX);
GPIOPinConfigure(GPIO_PB7_SSI2TX);
GPIOPinTypeSSI(GPIO_PORTB_BASE, GPIO_PIN_4 | GPIO_PIN_6 | GPIO_PIN_7);
/* Configure IRQ pin */
GPIOPinTypeGPIOInput(GPIO_PORTB_BASE, GPIO_PIN_2);
GPIOIntTypeSet(GPIO_PORTB_BASE, GPIO_PIN_2, GPIO_FALLING_EDGE);
/* Configure EN pin */
GPIOPinTypeGPIOOutput(GPIO_PORTB_BASE, GPIO_PIN_5);
GPIOPinWrite(GPIO_PORTB_BASE, GPIO_PIN_5, 0);
/* Configure CS pin */
GPIOPinTypeGPIOOutput(GPIO_PORTE_BASE, GPIO_PIN_0);
GPIOPinWrite(GPIO_PORTE_BASE, GPIO_PIN_0, 0);
/* Call necessary SPI init functions */
SPI_init();
EK_TM4C123GXL_initDMA();
/* Initialize WiFi driver */
WiFi_init();
}
示例5: EEPROM_Init
void EEPROM_Init()
{
SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI1);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
GPIOPinConfigure(GPIO_PD0_SSI1CLK);
GPIOPinConfigure(GPIO_PD1_SSI1FSS);
GPIOPinConfigure(GPIO_PD2_SSI1RX);
GPIOPinConfigure(GPIO_PD3_SSI1TX);
GPIOPinTypeGPIOOutput(GPIO_PORTD_BASE,GPIO_PIN_CS);
GPIOPinTypeSSI(GPIO_PORTD_BASE, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2|GPIO_PIN_3);
SSIConfigSetExpClk(SSI1_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 1000, 8);
SSIEnable(SSI1_BASE);
memset(_eepromcachestr,0,EEPROMADDRSTRLEN+1);
_iseepromenabled = EEPROM_Test();
}
示例6: BSP_SSI0_Init
/* ------------------------------------------------------------------------------------------------------
* ssi0_Init()
*
* Description : SPI sysctl init function.
*
* Argument(s) : none.
*
*/
void BSP_SSI0_Init(void)
{
SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
SSIDisable(SSI0_BASE); /* Disable SSI0.*/
GPIOPinTypeSSI(GPIO_PORTA_BASE, /* Configure the SPI port*/
GPIO_PIN_2|GPIO_PIN_4|GPIO_PIN_5);
GPIOPadConfigSet(GPIO_PORTA_BASE,
GPIO_PIN_2|GPIO_PIN_4|GPIO_PIN_5,
GPIO_STRENGTH_4MA,
GPIO_PIN_TYPE_STD_WPU);
GPIOPinTypeGPIOOutput(GPIO_PORTA_BASE, GPIO_PIN_6); /* Configure the CS port*/
GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_6, GPIO_STRENGTH_4MA,
GPIO_PIN_TYPE_STD_WPU);
SELECT();
DESELECT(); /* Deassert the SSI0 chip select */
SSIConfigSetExpClk(SSI0_BASE, /* Configure the SSI0 port */
SysCtlClockGet(),
SSI_FRF_MOTO_MODE_0,
SSI_MODE_MASTER, 400000, 8);
SSIEnable(SSI0_BASE); /* Enable SSI0.*/
}
示例7: main
int main(void)
{
uint32_t ui32Index;
uint32_t ui32Data;
SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_16MHZ);
SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
GPIOPinConfigure(GPIO_PA2_SSI0CLK);
GPIOPinConfigure(GPIO_PA3_SSI0FSS);
GPIOPinConfigure(GPIO_PA5_SSI0TX);
GPIOPinTypeSSI(GPIO_PORTA_BASE,GPIO_PIN_5|GPIO_PIN_3|GPIO_PIN_2);
SSIConfigSetExpClk(SSI0_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 10000, 16);
SSIEnable(SSI0_BASE);
while(1)
{
for(ui32Index = 0; ui32Index < NUM_SSI_DATA; ui32Index++)
{
ui32Data = (Reverse(pui8DataTx[ui32Index]) << 8) + (1 << ui32Index);
SSIDataPut(SSI0_BASE, ui32Data);
while(SSIBusy(SSI0_BASE))
{
}
}
}
}
示例8: init_pins
void init_pins()
{
//PORT A - SDHC Card
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
//set output: SD_SCK, SD_CS, SD_MOSI
GPIOSetOutput(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5);
//Set Input: SD_MISO
GPIOSetInput(GPIO_PORTA_BASE, GPIO_PIN_4);
//Initialize pins: SD_SCK <- LOW, SD_CS <- HIGH, SD_MOSI <- LOW
GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5, GPIO_PIN_3);
//Set SD_CLK, SD_MISO, SD_MOSI as SSI pins
GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_4 | GPIO_PIN_5);
//Port B - RTC
//Enable Port B
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
//Set pin type as I2C
GPIOPinTypeI2C(GPIO_PORTB_BASE, GPIO_PIN_2 | GPIO_PIN_3);
//Port D - LCD
//TODO: Initialize LCD pins
//Port E - SSI1 , VS0_BSYNC, VS0_RESET, VS0_DREQ, VS0_CS
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);
//Set Output: VS_CLK, VS0_CS, VS_MOSI, VS0_BSYNC, VS0_RESET
GPIOSetOutput(GPIO_PORTE_BASE, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_6);
//Set Input: VS_MISO, VS0_DREQ
GPIOSetInput(GPIO_PORTE_BASE, GPIO_PIN_2 | GPIO_PIN_5);
//Initialize Pins: VS_CLK <- LOW, VS0_CS <- HIGH, VS_MOSI <- LOW, VS0_BSYNC <- HIGH, VS0_RESET <- LOW,
GPIOPinWrite(GPIO_PORTE_BASE, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_6, GPIO_PIN_1 | GPIO_PIN_4);
//Set VS_CLK, VS_MOSI, VS_MISO as SSI pins
GPIOPinTypeSSI(GPIO_PORTE_BASE, GPIO_PIN_0 | GPIO_PIN_2 | GPIO_PIN_3);
//Port F -VS1_BSYNC, VS1_RESET, VS1_DREQ, VS1_CS
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
//Set Output: VS1_RESET, VS1_BSYNC, VS1_CS
GPIOSetOutput(GPIO_PORTF_BASE, GPIO_PIN_0 | GPIO_PIN_2 | GPIO_PIN_3);
//Set Input: VS1_DREQ
GPIOSetInput(GPIO_PORTF_BASE, GPIO_PIN_1);
//Initialize Pins: VS0_RESET <- LOW, VS0_BSYNC <- HIGH, VS1_CS <- HIGH
GPIOPinWrite(GPIO_PORTE_BASE, GPIO_PIN_0 | GPIO_PIN_2 | GPIO_PIN_3, GPIO_PIN_2 | GPIO_PIN_3);
return;
}
示例9: RIT128x96x4Init
//*****************************************************************************
//
//! Initialize the OLED display.
//!
//! \param ulFrequency specifies the SSI Clock Frequency to be used.
//!
//! This function initializes the SSI interface to the OLED display and
//! configures the SSD1329 controller on the panel.
//!
//! \return None.
//
//*****************************************************************************
void
RIT128x96x4Init(unsigned long ulFrequency)
{
unsigned long ulIdx;
// Initialize the semaphore
OS_InitSemaphore(&oLEDFree, 1);
//
// Enable the SSI0 and GPIO port blocks as they are needed by this driver.
//
SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIO_OLEDDC);
//
// Configure the SSI0CLK and SSIOTX pins for SSI operation.
//
GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5);
GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5,
GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD_WPU);
//
// Configure the GPIO port pin used as a D/Cn signal for OLED device,
// and the port pin used to enable power to the OLED panel.
//
GPIOPinTypeGPIOOutput(GPIO_OLEDDC_BASE, GPIO_OLEDDC_PIN | GPIO_OLEDEN_PIN);
GPIOPadConfigSet(GPIO_OLEDDC_BASE, GPIO_OLEDDC_PIN | GPIO_OLEDEN_PIN,
GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD);
GPIOPinWrite(GPIO_OLEDDC_BASE, GPIO_OLEDDC_PIN | GPIO_OLEDEN_PIN,
GPIO_OLEDDC_PIN | GPIO_OLEDEN_PIN);
HWREGBITW(&g_ulSSIFlags, FLAG_DC_HIGH) = 1;
//
// Configure and enable the SSI0 port for master mode.
//
RIT128x96x4Enable(ulFrequency);
//
// Clear the frame buffer.
//
RIT128x96x4Clear();
//
// Initialize the SSD1329 controller. Loop through the initialization
// sequence array, sending each command "string" to the controller.
//
for(ulIdx = 0; ulIdx < sizeof(g_pucRIT128x96x4Init);
ulIdx += g_pucRIT128x96x4Init[ulIdx] + 1)
{
//
// Send this command.
//
RITWriteCommand(g_pucRIT128x96x4Init + ulIdx + 1,
g_pucRIT128x96x4Init[ulIdx] - 1);
}
}
示例10: initSSI
//*************************************************//
//initSSI
//Prototype: void initSSI(void)
//Description: init SPI module for communicate with vs1011e.
//Returns: None.
//*************************************************//
void initSSI(void)
{
SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_4 | GPIO_PIN_5);
GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_4| GPIO_PIN_5, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD_WPU);
SSIConfigSetExpClk(SSI0_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 2000000, 8);
SSIEnable(SSI0_BASE);
}
示例11: OrbitOledHostInit
void
OrbitOledHostInit()
{
DelayInit();
/* Initialize SSI port 3.
*/
SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI3);
GPIOPinTypeSSI(SCK_OLEDPort, SCK_OLED_PIN);
GPIOPinTypeSSI(SDI_OLEDPort, SDI_OLED_PIN);
GPIOPinConfigure(SDI_OLED);
GPIOPinConfigure(SCK_OLED);
SSIClockSourceSet(SSI3_BASE, SSI_CLOCK_SYSTEM);
SSIConfigSetExpClk(SSI3_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 8000000, 8);
SSIEnable(SSI3_BASE);
/* Make power control pins be outputs with the supplies off
*/
GPIOPinWrite(VBAT_OLEDPort, VBAT_OLED, VBAT_OLED);
GPIOPinWrite(VDD_OLEDPort, VDD_OLED, VDD_OLED);
GPIOPinTypeGPIOOutput(VBAT_OLEDPort, VBAT_OLED); //VDD power control (1=off)
GPIOPinTypeGPIOOutput(VDD_OLEDPort, VDD_OLED); //VBAT power control (1=off)
/* Make the Data/Command select, Reset, and SSI CS pins be outputs.
* The nDC_OLED pin is PD7 an is a special GPIO (it is an NMI pin)
* Therefore, we must unlock it first:
* 1. Write 0x4C4F434B to GPIOLOCK register to unlock the GPIO Commit register
* 2. Write to appropriate bit in the Commit Register (bit 7)
* 3. Re-lock the GPIOLOCK register
*/
HWREG(GPIO_PORTD_BASE + GPIO_O_LOCK) = 0x4C4F434B; // unlock
HWREG(GPIO_PORTD_BASE + GPIO_O_CR) |= 1 << 7; // allow writes
HWREG(GPIO_PORTD_BASE + GPIO_O_LOCK) = 0x0; // re-lock
GPIOPinWrite(nDC_OLEDPort, nDC_OLED, nDC_OLED);
GPIOPinTypeGPIOOutput(nDC_OLEDPort, nDC_OLED);
GPIOPinWrite(nDC_OLEDPort, nDC_OLED, nDC_OLED);
GPIOPinWrite(nRES_OLEDPort, nRES_OLED, nRES_OLED);
GPIOPinTypeGPIOOutput(nRES_OLEDPort, nRES_OLED);
GPIOPinWrite(nCS_OLEDPort, nCS_OLED, nCS_OLED);
GPIOPinTypeGPIOOutput(nCS_OLEDPort, nCS_OLED);
}
示例12: EKS_LM4F232_initSPI
/*
* ======== EKS_LM4F232_initSPI ========
*/
Void EKS_LM4F232_initSPI(Void)
{
/* SPI1
SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI1);
Need to unlock PF0
HWREG(GPIO_PORTF_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY;
HWREG(GPIO_PORTF_BASE + GPIO_O_CR) |= GPIO_PIN_0;
GPIOPinConfigure(GPIO_PF0_SSI1RX);
GPIOPinConfigure(GPIO_PF1_SSI1TX);
GPIOPinConfigure(GPIO_PF2_SSI1CLK);
GPIOPinConfigure(GPIO_PF3_SSI1FSS);
GPIOPinTypeSSI(GPIO_PORTF_BASE, GPIO_PIN_0 | GPIO_PIN_1 |
GPIO_PIN_2 | GPIO_PIN_3);
HWREG(GPIO_PORTF_BASE + GPIO_O_LOCK) = GPIO_LOCK_M;*/
/* SSI0 */
SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0);
GPIOPinConfigure(GPIO_PA2_SSI0CLK);
GPIOPinConfigure(GPIO_PA3_SSI0FSS);
GPIOPinConfigure(GPIO_PA4_SSI0RX);
GPIOPinConfigure(GPIO_PA5_SSI0TX);
GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_3 |
GPIO_PIN_4 | GPIO_PIN_5);
/* SSI3 */
SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI3);
GPIOPinConfigure(GPIO_PK0_SSI3CLK);
GPIOPinConfigure(GPIO_PK1_SSI3FSS);
GPIOPinConfigure(GPIO_PK2_SSI3RX);
GPIOPinConfigure(GPIO_PK3_SSI3TX);
GPIOPinTypeSSI(GPIO_PORTK_BASE, GPIO_PIN_0 | GPIO_PIN_1 |
GPIO_PIN_2 | GPIO_PIN_3);
EKS_LM4F232_initDMA();
SPI_init();
}
示例13: SysCtrlPeripheralEnable
void Spi::enable(uint32_t baudrate)
{
GpioConfig& miso = miso_.getGpioConfig();
GpioConfig& mosi = mosi_.getGpioConfig();
GpioConfig& clk = clk_.getGpioConfig();
// GpioConfig& ncs = ncs_.getGpioConfig();
// Store baudrate in configuration
if (baudrate != 0) {
config_.baudrate = baudrate;
}
// Enable peripheral except in deep sleep modes (e.g. LPM1, LPM2, LPM3)
SysCtrlPeripheralEnable(config_.peripheral);
SysCtrlPeripheralSleepEnable(config_.peripheral);
SysCtrlPeripheralDeepSleepDisable(config_.peripheral);
// Reset peripheral previous to configuring it
SSIDisable(config_.base);
// Set IO clock as SPI0 clock source
SSIClockSourceSet(config_.base, config_.clock);
// Configure the MISO, MOSI, CLK and nCS pins as peripheral
IOCPinConfigPeriphInput(miso.port, miso.pin, miso.ioc);
IOCPinConfigPeriphOutput(mosi.port, mosi.pin, mosi.ioc);
IOCPinConfigPeriphOutput(clk.port, clk.pin, clk.ioc);
// IOCPinConfigPeriphOutput(ncs.port, ncs.pin, ncs.ioc);
// Configure MISO, MOSI, CLK and nCS GPIOs
GPIOPinTypeSSI(miso.port, miso.pin);
GPIOPinTypeSSI(mosi.port, mosi.pin);
GPIOPinTypeSSI(clk.port, clk.pin);
// GPIOPinTypeSSI(ncs.port, ncs.pin);
// Configure the SPI0 clock
SSIConfigSetExpClk(config_.base, SysCtrlIOClockGet(), config_.protocol, \
config_.mode, config_.baudrate, config_.datawidth);
// Enable the SPI0 module
SSIEnable(config_.base);
}
示例14: setup
void setup()
{
//--------------------- GENERAL ---------------------
// Enable lazy stacking for interrupt handlers. This allows floating-point
// instructions to be used within interrupt handlers, but at the expense of
// extra stack usage.
ROM_FPUEnable();
ROM_FPULazyStackingEnable();
// Set the clocking to run directly from the crystal.
ROM_SysCtlClockSet(SYSCTL_SYSDIV_1 | SYSCTL_USE_OSC | SYSCTL_OSC_MAIN |
SYSCTL_XTAL_16MHZ);
ROM_IntMasterEnable();
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
ROM_GPIOPinTypeGPIOOutput(GPIO_PORTA_BASE, GPIO_PIN_6);
//--------------------- UART ---------------------
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);
GPIOPinConfigure(GPIO_PA0_U0RX);
GPIOPinConfigure(GPIO_PA1_U0TX);
ROM_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
// Configure the UART for 115,200, 8-N-1 operation.
ROM_UARTConfigSetExpClk(UART0_BASE, ROM_SysCtlClockGet(), 115200,
(UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE));
// Enable the UART interrupt.
ROM_IntEnable(INT_UART0);
ROM_UARTIntEnable(UART0_BASE, UART_INT_RX | UART_INT_RT);
//--------------------- SSI ---------------------
SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0);
GPIOPinConfigure(GPIO_PA2_SSI0CLK);
GPIOPinConfigure(GPIO_PA3_SSI0FSS);
GPIOPinConfigure(GPIO_PA4_SSI0RX);
GPIOPinConfigure(GPIO_PA5_SSI0TX);
GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_5 | GPIO_PIN_4 | GPIO_PIN_3 | GPIO_PIN_2);
SSIConfigSetExpClk(SSI0_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 10000, 8);
SSIEnable(SSI0_BASE);
}
示例15: SPI_init
void SPI_init(){
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
GPIOPinTypeSSI(GPIO_PORTA_BASE,GPIO_PIN_2|GPIO_PIN_4|GPIO_PIN_5);
GPIOPinConfigure(GPIO_PA2_SSI0CLK);
GPIOPinConfigure(GPIO_PA4_SSI0RX);
GPIOPinConfigure(GPIO_PA5_SSI0TX);
SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0);
SSIClockSourceSet(SSI0_BASE,SSI_CLOCK_PIOSC);
SSIConfigSetExpClk(SSI0_BASE,SysCtlClockGet(),SSI_FRF_MOTO_MODE_0,SSI_MODE_MASTER,6000000,8);
SSIEnable(SSI0_BASE);
}