C++ DRV_Reg32函数代码示例

void GIF_GetInfo(gif_info_struct *out)
{
	kal_uint32 reg;

	// Image descriptor
	reg = DRV_Reg32(GIF_IMG_REG_1);
	out->height = (kal_uint16)(reg & 0xFFFF); 
	out->width = (kal_uint16)(reg >> 16);
	
	reg = DRV_Reg32(GIF_IMG_REG_2);
	out->y = (kal_uint16)(reg & 0xFFFF); 
	out->x = (kal_uint16)(reg >> 16);
	
	reg = DRV_Reg32(GIF_IMG_REG_3);
	out->LCT_size = (reg & GIF_IMG_REG3_LCT_SIZE); 
	out->interlace = (reg & GIF_IMG_REG3_LCT_INTERLACE) >> 6;
	out->LCT_flag = (reg & GIF_IMG_REG3_LCT_FLG) >> 7;

	// Logical screen descriptor
	reg = DRV_Reg32(GIF_LSD_REG_1);
	out->lheight = (kal_uint16)(reg & 0xFFFF); 
	out->lwidth = (kal_uint16)(reg >> 16);

	reg = DRV_Reg32(GIF_LSD_REG_2);
	out->bg = (reg & GIF_LSD2_BG) >> 8; 
	out->GCT_size = (reg & GIF_LSD2_GCT_SIZE) >> 16; 	
	out->bpp = (reg & GIF_LSD2_BPP) >> 20; 
	out->GCT_flag= (reg & GIF_LSD2_GCT_FLG) >> 23;
	
}

void mtk_wdt_init(void)
{
    unsigned int tmp;
    unsigned int interval_val = DRV_Reg32(MTK_WDT_INTERVAL);
    mtk_wdt_mode_config(FALSE, FALSE, FALSE, FALSE, FALSE);
    printf("UB wdt init\n");

    /* Update interval register value and check reboot flag */
    if( (interval_val & RGU_TRIGGER_RESET_MASK) == IS_POWER_ON_RESET )
        is_rgu_trigger_rst = 0; // Power off and power on reset
    else
        is_rgu_trigger_rst = 1; // RGU trigger reset

    interval_val &= ~(RGU_TRIGGER_RESET_MASK|MAGIC_NUM_MASK);
    interval_val |= (U_BOOT_MAGIC|IS_POWER_ON_RESET);

    /* Write back INTERVAL REG */
    DRV_WriteReg32(MTK_WDT_INTERVAL, interval_val);
    /* Setting timeout 10s */
    mtk_wdt_set_time_out_value(10);

    /*set spm_sysrst & pcm_wdt_rst to be reset mode*/
    tmp = DRV_Reg32(MTK_WDT_REQ_IRQ_EN);
    tmp |= MTK_WDT_REQ_IRQ_EN_KEY;
    tmp &= ~(MTK_WDT_REQ_IRQ_EN_SPM | MTK_WDT_REQ_IRQ_EN_PCM);
    DRV_WriteReg32(MTK_WDT_REQ_IRQ_EN, tmp);

    mtk_wdt_mode_config(TRUE, TRUE, FALSE, FALSE, TRUE);
    mtk_wdt_restart();
}

static void __gpt_get_cnt(struct gpt_device *dev, unsigned int *ptr)
{
    *ptr = DRV_Reg32(dev->base_addr + GPT_CNT);
    if (dev->features & GPT_FEAT_64_BIT) {
        *(++ptr) = DRV_Reg32(dev->base_addr + GPT_CNTH);
    } 
}

static void mt_fh_hal_popod_save(void)
{
    const unsigned int  pll_id  = FH_MAIN_PLLID;

	FH_MSG_DEBUG("EN: %s",__func__);

	//disable maipll SSC mode
	if(g_fh_pll[pll_id].fh_status == FH_FH_ENABLE_SSC){
    	unsigned int	fh_dds = 0;
    	unsigned int	pll_dds = 0;
    	const unsigned int  reg_cfg = g_reg_cfg[pll_id];

	    //only when SSC is enable, turn off MAINPLL hopping
		fh_set_field(reg_cfg, FH_FRDDSX_EN, 0);  //disable SSC mode
		fh_set_field(reg_cfg, FH_SFSTRX_EN, 0);  //disable dvfs mode
		fh_set_field(reg_cfg, FH_FHCTLX_EN, 0);  //disable hopping control

		pll_dds =  (DRV_Reg32(g_reg_dds[pll_id])) & MASK21b;
		fh_dds	=  (DRV_Reg32(g_reg_mon[pll_id])) & MASK21b;

		FH_MSG("Org pll_dds:%x fh_dds:%x",pll_dds,fh_dds);

        wait_dds_stable(pll_dds, g_reg_mon[pll_id], 100);

		//write back to ncpo
		fh_write32(g_reg_pll_con1[pll_id],
		    (fh_read32(g_reg_dds[pll_id])&MASK21b)|(fh_read32(MAINPLL_CON1)&0xFFE00000)|(BIT32));
		FH_MSG("MAINPLL_CON1: 0x%08x",(fh_read32(g_reg_pll_con1[pll_id])&MASK21b));

		// switch to register control
		fh_switch2fhctl(pll_id,0);
		mb();
	}
}

static ssize_t cpu_ss_mode_write(struct file *file, const char *buffer, unsigned long count, void *data)
{
    int len = 0, mode = 0;
    char desc[32];

    len = (count < (sizeof(desc) - 1)) ? count : (sizeof(desc) - 1);
    if (copy_from_user(desc, buffer, len))
    {
        return 0;
    }
    desc[len] = '\0';

    if (sscanf(desc, "%d", &mode) == 1)
    {
        if (mode)
        {
            printk("[%s]: config cpu speed switch mode = ARMPLL\n", __FUNCTION__);
            mt65xx_reg_sync_writel((DRV_Reg32(TOP_CKMUXSEL) | 0x0004), TOP_CKMUXSEL);
        }
        else
        {
            printk("[%s]: config cpu speed switch mode = CLKSQ\n", __FUNCTION__);
            mt65xx_reg_sync_writel((DRV_Reg32(TOP_CKMUXSEL) & 0x0ff3), TOP_CKMUXSEL);
        }

        return count;
    }
    else
    {
        printk("[%s]: bad argument!! should be \"1\" or \"0\"\n", __FUNCTION__);
    }

    return -EINVAL;
}

int mt_cpu_ss_thread_handler(void *unused)
{
    kal_uint32 flag = 0;

    do
    {
        ktime_t ktime = ktime_set(mt_cpu_ss_period_s, mt_cpu_ss_period_ns);

        wait_event_interruptible(mt_cpu_ss_timer_waiter, mt_cpu_ss_timer_flag != 0);
        mt_cpu_ss_timer_flag = 0;

        if (!flag)
        {
            mt65xx_reg_sync_writel((DRV_Reg32(TOP_CKMUXSEL) & 0x0ff3), TOP_CKMUXSEL);
            flag = 1;
        }
        else
        {
            mt65xx_reg_sync_writel((DRV_Reg32(TOP_CKMUXSEL) | 0x0004), TOP_CKMUXSEL);
            flag = 0;
        }

        if (mt_cpu_ss_debug_mode)
            printk("[%s]: TOP_CKMUXSEL = 0x%x\n", __FUNCTION__, DRV_Reg32(TOP_CKMUXSEL));

        hrtimer_start(&mt_cpu_ss_timer, ktime, HRTIMER_MODE_REL);

    } while (!kthread_should_stop());

    return 0;
}

void mt_mempll_ssc(void)
{
#if !defined(__FPGA__) 
    kal_uint32 reg_val;

    // MT6290(M), Not E1, Because MT6290(M)E1 has WMHEC5471
    if ((DRV_Reg32(HW_CODE_VERSION) == 0x00006290) && (DRV_Reg32(HW_VERSION) != 0x0000CA00)) {
        reg_val = DRV_Reg32(REG_MDCLKCTL_EMIDDS_FH_CTL2) & ~(EMIDDS_FH_CTL2_FRDDS_DNLMT_MASK | EMIDDS_FH_CTL2_FRDDS_UPLMT_MASK);
        if (TRUE == is_mt6290m) {
            // -8%. For PCW is equal to 25MHz, down limit is 2 MHz, Up limit is 0 MHz
            //reg_val |= EMIDDS_FH_CTL2_FRDDS_DNLMT(0x9E) | EMIDDS_FH_CTL2_FRDDS_UPLMT(0x0);
            // -4%. For PCW is equal to 25MHz, down limit is 2 MHz, Up limit is 0 MHz
            reg_val |= EMIDDS_FH_CTL2_FRDDS_DNLMT(0x4F) | EMIDDS_FH_CTL2_FRDDS_UPLMT(0x0);
        } else {
            // -8%. For PCW is equal to 27.79167MHz, down limit is 2.2 MHz, Up limit is 0 MHz
            //reg_val |= EMIDDS_FH_CTL2_FRDDS_DNLMT(0xB0) | EMIDDS_FH_CTL2_FRDDS_UPLMT(0x0);
            // -4%. For PCW is equal to 27.79167MHz, down limit is 1.1 MHz, Up limit is 0 MHz
            reg_val |= EMIDDS_FH_CTL2_FRDDS_DNLMT(0x58) | EMIDDS_FH_CTL2_FRDDS_UPLMT(0x0);
        }
        DRV_WriteReg32(REG_MDCLKCTL_EMIDDS_FH_CTL2, reg_val);
        // Time Step is 0.5 us, Frequency Step is ~0.1MHz
        reg_val = DRV_Reg32(REG_MDCLKCTL_EMIDDS_FH_CTL1) & ~(EMIDDS_FH_CTL1_EMIDDS_FRDDS_DTS_MASK | EMIDDS_FH_CTL1_EMIDDS_FRDDS_DYS_MASK);
        reg_val |= EMIDDS_FH_CTL1_EMIDDS_FSM_EN | EMIDDS_FH_CTL1_EMIDDS_FRDDS_EN | \
                    EMIDDS_FH_CTL1_EMIDDS_FRDDS_DTS(0) | EMIDDS_FH_CTL1_EMIDDS_FRDDS_DYS(0);
        DRV_WriteReg32(REG_MDCLKCTL_EMIDDS_FH_CTL1, reg_val);
        // We need to write EMIDDS_CTL to mask sure that previous settings take effect
        reg_val = DRV_Reg32(REG_MDCLKCTL_EMIDDS_CTL) | EMIDDS_SDM_PCW_CHG;
        DRV_WriteReg32_NPW(REG_MDCLKCTL_EMIDDS_CTL, reg_val);

        Data_Mem_Barrier();
    }
#endif // end if !defined(__FPGA__)
}

static int mt_fh_hal_dfs_mpll(unsigned int target_dds)
{
	unsigned long 	flags = 0;
	const unsigned int  pll_id  = FH_M_PLLID;
	const unsigned int  reg_cfg = g_reg_cfg[pll_id];

	FH_MSG("%s, current dds(MPLL_CON1): 0x%x, target dds %d",
	    __func__,(fh_read32(g_reg_pll_con1[pll_id])&MASK21b),
	    target_dds);

	spin_lock_irqsave(&g_fh_lock, flags);

	if(g_fh_pll[pll_id].fh_status == FH_FH_ENABLE_SSC){
        unsigned int	pll_dds = 0;
        unsigned int	fh_dds  = 0;

		fh_set_field(reg_cfg, FH_FRDDSX_EN, 0);  //disable SSC mode
		fh_set_field(reg_cfg, FH_SFSTRX_EN, 0);  //disable dvfs mode
		fh_set_field(reg_cfg, FH_FHCTLX_EN, 0);  //disable hopping control

		pll_dds =  (DRV_Reg32(g_reg_dds[pll_id])) & MASK21b;
		fh_dds	=  (DRV_Reg32(g_reg_mon[pll_id])) & MASK21b;

		FH_MSG(">p:f< %x:%x",pll_dds,fh_dds);

        wait_dds_stable(pll_dds, g_reg_mon[pll_id], 100);
	}

	mt_fh_hal_dvfs(pll_id, target_dds);

	if(g_fh_pll[pll_id].fh_status == FH_FH_ENABLE_SSC){
	    const struct freqhopping_ssc* p_setting = &ssc_mpll_setting[2];

		fh_set_field(reg_cfg, FH_FRDDSX_EN, 0);  //disable SSC mode
		fh_set_field(reg_cfg, FH_SFSTRX_EN, 0);  //disable dvfs mode
		fh_set_field(reg_cfg, FH_FHCTLX_EN, 0);  //disable hopping control

		fh_sync_ncpo_to_fhctl_dds(pll_id);

		FH_MSG("Enable mpll SSC mode");
		FH_MSG("DDS: 0x%08x", (fh_read32(g_reg_dds[pll_id])&MASK21b));

		fh_set_field(reg_cfg,MASK_FRDDSX_DYS,p_setting->df);
		fh_set_field(reg_cfg,MASK_FRDDSX_DTS,p_setting->dt);

		fh_write32(g_reg_updnlmt[pll_id],
		    (PERCENT_TO_DDSLMT((fh_read32(g_reg_dds[pll_id])&MASK21b), p_setting->lowbnd) << 16));
		FH_MSG("UPDNLMT: 0x%08x", fh_read32(g_reg_updnlmt[pll_id]));

		fh_switch2fhctl(pll_id, 1);

		fh_set_field(reg_cfg, FH_FRDDSX_EN, 1);  //enable SSC mode
		fh_set_field(reg_cfg, FH_FHCTLX_EN, 1);  //enable hopping control

		FH_MSG("CFG: 0x%08x", fh_read32(reg_cfg));
	}
	spin_unlock_irqrestore(&g_fh_lock, flags);

    return 0;
}

static void spm_wdt_init(void)
{

   unsigned int tmp;
   // set scpsys reset mode , not trigger irq
   tmp = DRV_Reg32(MTK_WDT_REQ_MODE);
   tmp |=  MTK_WDT_REQ_MODE_KEY;
   tmp |= (MTK_WDT_REQ_MODE_SPM_SCPSYS);
   DRV_WriteReg32(MTK_WDT_REQ_MODE,tmp);

   tmp = DRV_Reg32(MTK_WDT_REQ_IRQ_EN);
   tmp |= MTK_WDT_REQ_IRQ_KEY;
   tmp &= ~(MTK_WDT_REQ_IRQ_SPM_SCPSYS_EN);
   DRV_WriteReg32(MTK_WDT_REQ_IRQ_EN,tmp);
   
	   
   printk( "mtk_wdt_init [MTK_WDT] not use RGU WDT use_SPM_WDT!! ********\n" );
	   
   tmp = DRV_Reg32(MTK_WDT_MODE);
   tmp |= MTK_WDT_MODE_KEY;
   //disable wdt
   tmp &= (~(MTK_WDT_MODE_IRQ|MTK_WDT_MODE_ENABLE|MTK_WDT_MODE_DUAL_MODE));
	   
   // Bit 4: WDT_Auto_restart, this is a reserved bit, we use it as bypass powerkey flag.
   //	   Because HW reboot always need reboot to kernel, we set it always.
   tmp |= MTK_WDT_MODE_AUTO_RESTART;
   //BIt2  ext singal
   tmp |= MTK_WDT_MODE_EXTEN;
   DRV_WriteReg32(MTK_WDT_MODE,tmp);
	   
}

/*
 * mt6577_irq_mask_all: mask all IRQ lines. (This is ONLY used for the idle current measurement by the factory mode.)
 * @mask: pointer to struct mtk_irq_mask for storing the original mask value.
 * Return 0 for success; return negative values for failure.
 */
int mt6577_irq_mask_all(struct mtk_irq_mask *mask)
{
    unsigned long flags;

    if (mask) {

        mask->mask0 = DRV_Reg32(GIC_ICDISER0);
        mask->mask1 = DRV_Reg32(GIC_ICDISER1);
        mask->mask2 = DRV_Reg32(GIC_ICDISER2);
        mask->mask3 = DRV_Reg32(GIC_ICDISER3);
        mask->mask4 = DRV_Reg32(GIC_ICDISER4);

        DRV_WriteReg32(GIC_ICDICER0, 0xFFFFFFFF);
        DRV_WriteReg32(GIC_ICDICER1, 0xFFFFFFFF);
        DRV_WriteReg32(GIC_ICDICER2, 0xFFFFFFFF);
        DRV_WriteReg32(GIC_ICDICER3, 0xFFFFFFFF);
        DRV_WriteReg32(GIC_ICDICER4, 0xFFFFFFFF);
        dsb();

        mask->header = IRQ_MASK_HEADER;
        mask->footer = IRQ_MASK_FOOTER;

        return 0;
    } else {
        return -1;
    }
}

int mtk_wdt_swsysret_config(int bit,int set_value)
{
    unsigned int wdt_sys_val;
	spin_lock(&rgu_reg_operation_spinlock);
	printk("mtk_wdt_swsysret_config(0x%x,0x%x) \n",bit,set_value);
	switch(bit)
	{
	  case MTK_WDT_SWSYS_RST_MD_RST:
	  	   wdt_sys_val = DRV_Reg32(MTK_WDT_SWSYSRST);
		   printk("fwq2 before set wdt_sys_val =%x\n",wdt_sys_val);
    	   wdt_sys_val |= MTK_WDT_SWSYS_RST_KEY;
	  	   if(1==set_value)
	  	   {
	  	     wdt_sys_val |= MTK_WDT_SWSYS_RST_MD_RST;
	  	   }
		   if(0==set_value)
		   {
		     wdt_sys_val &= ~MTK_WDT_SWSYS_RST_MD_RST;
		   }
		   DRV_WriteReg32(MTK_WDT_SWSYSRST,wdt_sys_val);
	  	break;
	 case MTK_WDT_SWSYS_RST_MD_LITE_RST:
	 	   wdt_sys_val = DRV_Reg32(MTK_WDT_SWSYSRST);
		   printk("fwq2 before set wdt_sys_val =%x\n",wdt_sys_val);
    	   wdt_sys_val |= MTK_WDT_SWSYS_RST_KEY;
	  	   if(1==set_value)
	  	   {
	  	     wdt_sys_val |= MTK_WDT_SWSYS_RST_MD_LITE_RST;
	  	   }
		   if(0==set_value)
		   {
		     wdt_sys_val &= ~MTK_WDT_SWSYS_RST_MD_LITE_RST;
		   }
		   DRV_WriteReg32(MTK_WDT_SWSYSRST,wdt_sys_val);
	  	break;
		
	case 0x30000000:
		// io ring read non reset register
		wdt_sys_val = DRV_Reg32(MTK_WDT_NONRST_REG);
		printk("io ring read raw wdt_sys_val=0x%x",wdt_sys_val);
		//wdt_sys_val = wdt_sys_val & 0xFFFF;
		//printk("io ring read wdt_sys_val=0x%x",wdt_sys_val);
		spin_unlock(&rgu_reg_operation_spinlock);
		return wdt_sys_val;
	  	break;
	default:
		printk("do not handle this command \n");
	  	   
	}
	
	spin_unlock(&rgu_reg_operation_spinlock);
	mdelay(10);
	printk("mtk_wdt_swsysret_config done\n");
    return 0;
}

unsigned int hacc_do_aes(AES_OPS ops, unsigned char *src, unsigned char *dst, unsigned int size)
{
	unsigned int i;
	unsigned int *ds, *dt, *vt;

	/* make sure size is aligned to aes block size */
	if ((size % AES_BLK_SZ) != 0) {
		SMSG("[%s] size = %d is not %d bytes alignment\n", MOD, size, AES_BLK_SZ);
		return ERR_HACC_DATA_UNALIGNED;
	}

	vt = (unsigned int *)&hacc_ctx.cfg.config[0];

	/* erase src, cfg, out register */
	DRV_SetReg32(HACC_ACON2, HACC_AES_CLR);

	/* set init config */
	for (i = 0; i < AES_CFG_SZ; i += 4)
		DRV_WriteReg32(HACC_ACFG0 + i, *vt++);

	if (ops == AES_ENC)
		DRV_SetReg32(HACC_ACON, HACC_AES_ENC);
	else
		DRV_ClrReg32(HACC_ACON, HACC_AES_ENC);

	ds = (unsigned int *)src;
	dt = (unsigned int *)dst;

	do {
		/* fill in the data */
		for (i = 0; i < AES_BLK_SZ; i += 4)
			DRV_WriteReg32(HACC_ASRC0 + i, *ds++);

		/* start aes engine */
		DRV_SetReg32(HACC_ACON2, HACC_AES_START);

		/* wait for aes engine ready */
		while ((DRV_Reg32(HACC_ACON2) & HACC_AES_RDY) == 0)
			;

		/* read out the data */
		for (i = 0; i < AES_BLK_SZ; i += 4)
			*dt++ = DRV_Reg32(HACC_AOUT0 + i);

		if (size == 0)
			goto _end;

		size -= AES_BLK_SZ;

	} while (size != 0);

_end:

	return SEC_OK;
}

static void mt_auxadc_cal_prepare(void)
{
	unsigned int mt_auxadc_bgr=0;
	mt_auxadc_bgr = DRV_Reg32(AUXADC_BGR);
	printk("[adc_cali]:mt_auxadc_cal_prepare  get AUXADC_BGR 0x%04x \n",mt_auxadc_bgr);
	printk("[adc_cali]:mt_auxadc_cal_prepare  get AUXADC_TS_CON0 0x%04x \n",DRV_Reg32(AUXADC_TS_CON0));
	
	if(mt_auxadc_bgr&0xF0000000)
	{
		AUXADC_SET_BITS(((mt_auxadc_bgr&0xF0000000)>>16),AUXADC_TS_CON0);
	}

/*******************************************************************************
 * Function definitions
 *******************************************************************************/
void boot_init_bus()
{
    #if defined(MT6290_S00)
    // For E1 Chip, Add Arbitration Issue Patch When NFI + MSDC Coexist
    DRV_WriteReg32(BASE_MADDR_MDCFGCTL + 0x0030, DRV_Reg32(BASE_MADDR_MDCFGCTL + 0x0030) | (0x1 << 20)); // Set MD Own Bit
    DRV_WriteReg32(BASE_MADDR_APMISC + 0x0030, 0x00000000);
    DRV_WriteReg32(BASE_MADDR_MDCFGCTL + 0x0030, DRV_Reg32(BASE_MADDR_MDCFGCTL + 0x0030) & ~(0x1 << 20)); // Un-Set MD Own Bit
    #else
    
    #endif
}

void mrdump_check_ok(void)
{
    if ((DRV_Reg32(MRDUMP_SIG1_ADDR) == 0x5544524d) && 
	(DRV_Reg32(MRDUMP_SIG2_ADDR) == 0x3030504d)) 
      {
	  DRV_WriteReg32(MRDUMP_SIG1_ADDR, 0);
	  DRV_WriteReg32(MRDUMP_SIG2_ADDR, 0);
	  g_ddr_reserve_enable = 1;
	  g_ddr_reserve_success = 1;
	  print("[MRDUMP] DDR reserve mode success.\n");
      }
}