C++ DMA_BIT_MASK函数代码示例

};

static struct resource orion_ge00_resources[] = {
	{
		.name	= "ge00 irq",
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device orion_ge00 = {
	.name		= MV643XX_ETH_NAME,
	.id		= 0,
	.num_resources	= 1,
	.resource	= orion_ge00_resources,
	.dev		= {
		.coherent_dma_mask	= DMA_BIT_MASK(32),
	},
};

void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data,
			    unsigned long mapbase,
			    unsigned long irq,
			    unsigned long irq_err,
			    int tclk)
{
	fill_resources(&orion_ge00_shared, orion_ge00_shared_resources,
		       mapbase + 0x2000, SZ_16K - 1, irq_err);
	ge_complete(&orion_ge00_shared_data, tclk,
		    orion_ge00_resources, irq, &orion_ge00_shared,
		    eth_data, &orion_ge00);
}

	for (i = 0; i < 4; i++) {
		wrl(USB_WINDOW_CTRL(i), 0);
		wrl(USB_WINDOW_BASE(i), 0);
	}

	for (i = 0; i < dram->num_cs; i++) {
		const struct mbus_dram_window *cs = dram->cs + i;

		wrl(USB_WINDOW_CTRL(i), ((cs->size - 1) & 0xffff0000) |
					(cs->mbus_attr << 8) |
					(dram->mbus_dram_target_id << 4) | 1);
		wrl(USB_WINDOW_BASE(i), cs->base);
	}
}

static u64 ehci_orion_dma_mask = DMA_BIT_MASK(32);

static int ehci_orion_drv_probe(struct platform_device *pdev)
{
	struct orion_ehci_data *pd = pdev->dev.platform_data;
	const struct mbus_dram_target_info *dram;
	struct resource *res;
	struct usb_hcd *hcd;
	struct ehci_hcd *ehci;
	struct clk *clk;
	void __iomem *regs;
	int irq, err;
	enum orion_ehci_phy_ver phy_version;

	if (usb_disabled())
		return -ENODEV;

	omap_init_sham();
	omap_init_aes();
	omap_init_vout();
	am33xx_register_edma();
	am33xx_init_pcm();

	return 0;
}
arch_initcall(omap2_init_devices);

#define AM33XX_CPSW_BASE		(0x4A100000)
#define AM33XX_CPSW_MDIO_BASE		(0x4A101000)
#define AM33XX_CPSW_SS_BASE		(0x4A101200)
#define AM33XX_EMAC_MDIO_FREQ		(1000000)

static u64 am33xx_cpsw_dmamask = DMA_BIT_MASK(32);
/* TODO : Verify the offsets */
static struct cpsw_slave_data am33xx_cpsw_slaves[] = {
	{
		.slave_reg_ofs  = 0x208,
		.sliver_reg_ofs = 0xd80,
		.phy_id		= "0:00",
	},
	{
		.slave_reg_ofs  = 0x308,
		.sliver_reg_ofs = 0xdc0,
		.phy_id		= "0:01",
	},
};

static struct cpsw_platform_data am33xx_cpsw_pdata = {

		.start = DMACH_AC97_MICIN,
		.end   = DMACH_AC97_MICIN,
		.flags = IORESOURCE_DMA,
	},
	[4] = {
		.start = IRQ_AC97,
		.end   = IRQ_AC97,
		.flags = IORESOURCE_IRQ,
	},
};

static struct s3c_audio_pdata s3c_ac97_pdata = {
	.cfg_gpio = s5pv310_ac97_cfg_gpio,
};

static u64 s5pv310_ac97_dmamask = DMA_BIT_MASK(32);

struct platform_device s5pv310_device_ac97 = {
	.name             = "s3c-ac97",
	.id               = -1,
	.num_resources    = ARRAY_SIZE(s5pv310_ac97_resource),
	.resource         = s5pv310_ac97_resource,
	.dev = {
		.platform_data = &s3c_ac97_pdata,
		.dma_mask = &s5pv310_ac97_dmamask,
		.coherent_dma_mask = DMA_BIT_MASK(32),
	},
};

static struct resource s5pv310_rp_resource[] = {
};

    return !session_restart;
}

static struct musb_platform_ops dsps_ops = {
    .init		= dsps_musb_init,
    .exit		= dsps_musb_exit,

    .enable		= dsps_musb_enable,
    .disable	= dsps_musb_disable,

    .try_idle	= dsps_musb_try_idle,
    .set_mode	= dsps_musb_set_mode,
    .reset		= dsps_musb_reset,
};

static u64 musb_dmamask = DMA_BIT_MASK(32);

static int get_int_prop(struct device_node *dn, const char *s)
{
    int ret;
    u32 val;

    ret = of_property_read_u32(dn, s, &val);
    if (ret)
        return 0;
    return val;
}

static int get_musb_port_mode(struct device *dev)
{
    enum usb_dr_mode mode;

	for (stream = 0; stream < 2; stream++) {
		substream = pcm->streams[stream].substream;
		if (!substream)
			continue;

		buf = &substream->dma_buffer;
		if (!buf->area)
			continue;

		dma_free_writecombine(pcm->card->dev, buf->bytes,
				      buf->area, buf->addr);
		buf->area = NULL;
	}
}

static u64 sun4i_pcm_mask = DMA_BIT_MASK(32);

static int sun4i_pcm_new(struct snd_card *card,
			   struct snd_soc_dai *dai, struct snd_pcm *pcm)
{
	int ret = 0;
	
	if (!card->dev->dma_mask)
		card->dev->dma_mask = &sun4i_pcm_mask;
	if (!card->dev->coherent_dma_mask)
		card->dev->coherent_dma_mask = 0xffffffff;

	if (dai->driver->playback.channels_min) {
		ret = sun4i_pcm_preallocate_dma_buffer(pcm,
			SNDRV_PCM_STREAM_PLAYBACK);
		if (ret)

//.........这里部分代码省略.........
    result = platform_get_irq(pdev, 0);
    if (result < 0)
        goto err;

    p->irq = result;

    res_mix = platform_get_resource(pdev, IORESOURCE_MEM, 0);
    if (res_mix == NULL) {
        dev_err(&pdev->dev, "no 'reg' resource\n");
        result = -ENXIO;
        goto err;
    }

    res_agl = platform_get_resource(pdev, IORESOURCE_MEM, 1);
    if (res_agl == NULL) {
        dev_err(&pdev->dev, "no 'reg' resource\n");
        result = -ENXIO;
        goto err;
    }

    res_agl_prt_ctl = platform_get_resource(pdev, IORESOURCE_MEM, 3);
    if (res_agl_prt_ctl == NULL) {
        dev_err(&pdev->dev, "no 'reg' resource\n");
        result = -ENXIO;
        goto err;
    }

    p->mix_phys = res_mix->start;
    p->mix_size = resource_size(res_mix);
    p->agl_phys = res_agl->start;
    p->agl_size = resource_size(res_agl);
    p->agl_prt_ctl_phys = res_agl_prt_ctl->start;
    p->agl_prt_ctl_size = resource_size(res_agl_prt_ctl);


    if (!devm_request_mem_region(&pdev->dev, p->mix_phys, p->mix_size,
                                 res_mix->name)) {
        dev_err(&pdev->dev, "request_mem_region (%s) failed\n",
                res_mix->name);
        result = -ENXIO;
        goto err;
    }

    if (!devm_request_mem_region(&pdev->dev, p->agl_phys, p->agl_size,
                                 res_agl->name)) {
        result = -ENXIO;
        dev_err(&pdev->dev, "request_mem_region (%s) failed\n",
                res_agl->name);
        goto err;
    }

    if (!devm_request_mem_region(&pdev->dev, p->agl_prt_ctl_phys,
                                 p->agl_prt_ctl_size, res_agl_prt_ctl->name)) {
        result = -ENXIO;
        dev_err(&pdev->dev, "request_mem_region (%s) failed\n",
                res_agl_prt_ctl->name);
        goto err;
    }

    p->mix = (u64)devm_ioremap(&pdev->dev, p->mix_phys, p->mix_size);
    p->agl = (u64)devm_ioremap(&pdev->dev, p->agl_phys, p->agl_size);
    p->agl_prt_ctl = (u64)devm_ioremap(&pdev->dev, p->agl_prt_ctl_phys,
                                       p->agl_prt_ctl_size);
    spin_lock_init(&p->lock);

    skb_queue_head_init(&p->tx_list);
    skb_queue_head_init(&p->rx_list);
    tasklet_init(&p->tx_clean_tasklet,
                 octeon_mgmt_clean_tx_tasklet, (unsigned long)p);

    netdev->priv_flags |= IFF_UNICAST_FLT;

    netdev->netdev_ops = &octeon_mgmt_ops;
    netdev->ethtool_ops = &octeon_mgmt_ethtool_ops;

    mac = of_get_mac_address(pdev->dev.of_node);

    if (mac)
        memcpy(netdev->dev_addr, mac, ETH_ALEN);
    else
        eth_hw_addr_random(netdev);

    p->phy_np = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0);

    result = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
    if (result)
        goto err;

    netif_carrier_off(netdev);
    result = register_netdev(netdev);
    if (result)
        goto err;

    dev_info(&pdev->dev, "Version " DRV_VERSION "\n");
    return 0;

err:
    free_netdev(netdev);
    return result;
}

static struct ahci_platform_data exynos4_ahci_pdata = {
	.init = exynos4_ahci_init,
};

static struct resource exynos4_ahci_resource[] = {
	[0] = {
		.start	= EXYNOS4_PA_SATA,
		.end	= EXYNOS4_PA_SATA + SZ_64K - 1,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= EXYNOS4_IRQ_SATA,
		.end	= EXYNOS4_IRQ_SATA,
		.flags	= IORESOURCE_IRQ,
	},
};

static u64 exynos4_ahci_dmamask = DMA_BIT_MASK(32);

struct platform_device exynos4_device_ahci = {
	.name		= "ahci",
	.id		= -1,
	.resource	= exynos4_ahci_resource,
	.num_resources	= ARRAY_SIZE(exynos4_ahci_resource),
	.dev		= {
		.platform_data		= &exynos4_ahci_pdata,
		.dma_mask		= &exynos4_ahci_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(32),
	},
};

#include <asm/time.h>
#include <asm/netlogic/hal/nlm_hal.h>
#include <asm/netlogic/xlp_irq.h>
#include <asm/netlogic/xlp.h>

#define XLP_SOC_PCI_DRIVER 	"XLP SoC Driver"
#define DEV_IRT_INFO			0x3D

#define XLP_MAX_DEVICE			8
#define XLP_MAX_FUNC			8
#define MAX_NUM_UARTS			4
#define XLP_UART_PORTIO_OFFSET	0x1000

static struct plat_serial8250_port xlp_uart_port[MAX_NUM_UARTS];

static u64 xlp_dev_dmamask = DMA_BIT_MASK(32);

struct dev2drv {
	uint32_t 	devid;
	uint8_t 	drvname[16];
	uint8_t 	len;
	uint8_t 	id;
};

#ifdef CONFIG_SERIAL_8250
unsigned int xlp_uart_in(struct uart_port *p, int offset) {

	nlm_reg_t *mmio;
	unsigned int value;

	/* XLP uart does not need any mapping of regs 

static int __devinit fnic_probe(struct pci_dev *pdev,
				const struct pci_device_id *ent)
{
	struct Scsi_Host *host;
	struct fc_lport *lp;
	struct fnic *fnic;
	mempool_t *pool;
	int err;
	int i;
	unsigned long flags;

	/*
	 * Allocate SCSI Host and set up association between host,
	 * local port, and fnic
	 */
	lp = libfc_host_alloc(&fnic_host_template, sizeof(struct fnic));
	if (!lp) {
;
		err = -ENOMEM;
		goto err_out;
	}
	host = lp->host;
	fnic = lport_priv(lp);
	fnic->lport = lp;
	fnic->ctlr.lp = lp;

	snprintf(fnic->name, sizeof(fnic->name) - 1, "%s%d", DRV_NAME,
		 host->host_no);

	host->transportt = fnic_fc_transport;

	err = scsi_init_shared_tag_map(host, FNIC_MAX_IO_REQ);
	if (err) {
//		shost_printk(KERN_ERR, fnic->lport->host,
;
		goto err_out_free_hba;
	}

	/* Setup PCI resources */
	pci_set_drvdata(pdev, fnic);

	fnic->pdev = pdev;

	err = pci_enable_device(pdev);
	if (err) {
//		shost_printk(KERN_ERR, fnic->lport->host,
;
		goto err_out_free_hba;
	}

	err = pci_request_regions(pdev, DRV_NAME);
	if (err) {
//		shost_printk(KERN_ERR, fnic->lport->host,
;
		goto err_out_disable_device;
	}

	pci_set_master(pdev);

	/* Query PCI controller on system for DMA addressing
	 * limitation for the device.  Try 40-bit first, and
	 * fail to 32-bit.
	 */
	err = pci_set_dma_mask(pdev, DMA_BIT_MASK(40));
	if (err) {
		err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
		if (err) {
//			shost_printk(KERN_ERR, fnic->lport->host,
//				     "No usable DMA configuration "
;
			goto err_out_release_regions;
		}
		err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
		if (err) {
//			shost_printk(KERN_ERR, fnic->lport->host,
//				     "Unable to obtain 32-bit DMA "
;
			goto err_out_release_regions;
		}
	} else {
		err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40));
		if (err) {
//			shost_printk(KERN_ERR, fnic->lport->host,
//				     "Unable to obtain 40-bit DMA "
;
			goto err_out_release_regions;
		}
	}

	/* Map vNIC resources from BAR0 */
	if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
//		shost_printk(KERN_ERR, fnic->lport->host,
;
		err = -ENODEV;
		goto err_out_release_regions;
	}

	fnic->bar0.vaddr = pci_iomap(pdev, 0, 0);
	fnic->bar0.bus_addr = pci_resource_start(pdev, 0);
	fnic->bar0.len = pci_resource_len(pdev, 0);
//.........这里部分代码省略.........

// chip-specific constructor
// (see "Management of Cards and Components")
static int
snd_vortex_create(struct snd_card *card, struct pci_dev *pci, vortex_t ** rchip)
{
	vortex_t *chip;
	int err;
	static struct snd_device_ops ops = {
		.dev_free = snd_vortex_dev_free,
	};

	*rchip = NULL;

	// check PCI availability (DMA).
	if ((err = pci_enable_device(pci)) < 0)
		return err;
	if (pci_set_dma_mask(pci, DMA_BIT_MASK(32)) < 0 ||
	    pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32)) < 0) {
		dev_err(card->dev, "error to set DMA mask\n");
		pci_disable_device(pci);
		return -ENXIO;
	}

	chip = kzalloc(sizeof(*chip), GFP_KERNEL);
	if (chip == NULL) {
		pci_disable_device(pci);
		return -ENOMEM;
	}

	chip->card = card;

	// initialize the stuff
	chip->pci_dev = pci;
	chip->io = pci_resource_start(pci, 0);
	chip->vendor = pci->vendor;
	chip->device = pci->device;
	chip->card = card;
	chip->irq = -1;

	// (1) PCI resource allocation
	// Get MMIO area
	//
	if ((err = pci_request_regions(pci, CARD_NAME_SHORT)) != 0)
		goto regions_out;

	chip->mmio = pci_ioremap_bar(pci, 0);
	if (!chip->mmio) {
		dev_err(card->dev, "MMIO area remap failed.\n");
		err = -ENOMEM;
		goto ioremap_out;
	}

	/* Init audio core.
	 * This must be done before we do request_irq otherwise we can get spurious
	 * interrupts that we do not handle properly and make a mess of things */
	if ((err = vortex_core_init(chip)) != 0) {
		dev_err(card->dev, "hw core init failed\n");
		goto core_out;
	}

	if ((err = request_irq(pci->irq, vortex_interrupt,
			       IRQF_SHARED, KBUILD_MODNAME,
	                       chip)) != 0) {
		dev_err(card->dev, "cannot grab irq\n");
		goto irq_out;
	}
	chip->irq = pci->irq;

	pci_set_master(pci);
	// End of PCI setup.

	// Register alsa root device.
	if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
		goto alloc_out;
	}

	*rchip = chip;

	return 0;

      alloc_out:
	free_irq(chip->irq, chip);
      irq_out:
	vortex_core_shutdown(chip);
      core_out:
	iounmap(chip->mmio);
      ioremap_out:
	pci_release_regions(chip->pci_dev);
      regions_out:
	pci_disable_device(chip->pci_dev);
	//FIXME: this not the right place to unregister the gameport
	vortex_gameport_unregister(chip);
	kfree(chip);
	return err;
}

static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
    void __iomem *mem;
    struct ath_softc *sc;
    struct ieee80211_hw *hw;
    u8 csz;
    u32 val;
    int ret = 0;
    char hw_name[64];

    if (pci_enable_device(pdev))
        return -EIO;

    ret =  pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
    if (ret) {
        printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
        goto err_dma;
    }

    ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
    if (ret) {
        printk(KERN_ERR "ath9k: 32-bit DMA consistent "
               "DMA enable failed\n");
        goto err_dma;
    }

    /*
     * Cache line size is used to size and align various
     * structures used to communicate with the hardware.
     */
    pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
    if (csz == 0) {
        /*
         * Linux 2.4.18 (at least) writes the cache line size
         * register as a 16-bit wide register which is wrong.
         * We must have this setup properly for rx buffer
         * DMA to work so force a reasonable value here if it
         * comes up zero.
         */
        csz = L1_CACHE_BYTES / sizeof(u32);
        pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
    }
    /*
     * The default setting of latency timer yields poor results,
     * set it to the value used by other systems. It may be worth
     * tweaking this setting more.
     */
    pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);

    pci_set_master(pdev);

    /*
     * Disable the RETRY_TIMEOUT register (0x41) to keep
     * PCI Tx retries from interfering with C3 CPU state.
     */
    pci_read_config_dword(pdev, 0x40, &val);
    if ((val & 0x0000ff00) != 0)
        pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);

    ret = pci_request_region(pdev, 0, "ath9k");
    if (ret) {
        dev_err(&pdev->dev, "PCI memory region reserve error\n");
        ret = -ENODEV;
        goto err_region;
    }

    mem = pci_iomap(pdev, 0, 0);
    if (!mem) {
        printk(KERN_ERR "PCI memory map error\n") ;
        ret = -EIO;
        goto err_iomap;
    }

    hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
    if (!hw) {
        dev_err(&pdev->dev, "No memory for ieee80211_hw\n");
        ret = -ENOMEM;
        goto err_alloc_hw;
    }

    SET_IEEE80211_DEV(hw, &pdev->dev);
    pci_set_drvdata(pdev, hw);

    sc = hw->priv;
    sc->hw = hw;
    sc->dev = &pdev->dev;
    sc->mem = mem;

    /* Will be cleared in ath9k_start() */
    sc->sc_flags |= SC_OP_INVALID;

    ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc);
    if (ret) {
        dev_err(&pdev->dev, "request_irq failed\n");
        goto err_irq;
    }

    sc->irq = pdev->irq;

    ret = ath9k_init_device(id->device, sc, &ath_pci_bus_ops);
//.........这里部分代码省略.........

static int init_cc_resources(struct platform_device *plat_dev)
{
	struct resource *req_mem_cc_regs = NULL;
	struct cc_drvdata *new_drvdata;
	struct device *dev = &plat_dev->dev;
	struct device_node *np = dev->of_node;
	u32 signature_val;
	u64 dma_mask;
	int rc = 0;

	new_drvdata = devm_kzalloc(dev, sizeof(*new_drvdata), GFP_KERNEL);
	if (!new_drvdata)
		return -ENOMEM;

	platform_set_drvdata(plat_dev, new_drvdata);
	new_drvdata->plat_dev = plat_dev;

	new_drvdata->clk = of_clk_get(np, 0);
	new_drvdata->coherent = of_dma_is_coherent(np);

	/* Get device resources */
	/* First CC registers space */
	req_mem_cc_regs = platform_get_resource(plat_dev, IORESOURCE_MEM, 0);
	/* Map registers space */
	new_drvdata->cc_base = devm_ioremap_resource(dev, req_mem_cc_regs);
	if (IS_ERR(new_drvdata->cc_base))
		return PTR_ERR(new_drvdata->cc_base);

	dev_dbg(dev, "Got MEM resource (%s): %pR\n", req_mem_cc_regs->name,
		req_mem_cc_regs);
	dev_dbg(dev, "CC registers mapped from %pa to 0x%p\n",
		&req_mem_cc_regs->start, new_drvdata->cc_base);

	/* Then IRQ */
	new_drvdata->irq = platform_get_irq(plat_dev, 0);
	if (new_drvdata->irq < 0) {
		dev_err(dev, "Failed getting IRQ resource\n");
		return new_drvdata->irq;
	}

	rc = devm_request_irq(dev, new_drvdata->irq, cc_isr,
			      IRQF_SHARED, "arm_cc7x", new_drvdata);
	if (rc) {
		dev_err(dev, "Could not register to interrupt %d\n",
			new_drvdata->irq);
		return rc;
	}
	dev_dbg(dev, "Registered to IRQ: %d\n", new_drvdata->irq);

	init_completion(&new_drvdata->hw_queue_avail);

	if (!plat_dev->dev.dma_mask)
		plat_dev->dev.dma_mask = &plat_dev->dev.coherent_dma_mask;

	dma_mask = DMA_BIT_MASK(DMA_BIT_MASK_LEN);
	while (dma_mask > 0x7fffffffUL) {
		if (dma_supported(&plat_dev->dev, dma_mask)) {
			rc = dma_set_coherent_mask(&plat_dev->dev, dma_mask);
			if (!rc)
				break;
		}
		dma_mask >>= 1;
	}

	if (rc) {
		dev_err(dev, "Failed in dma_set_mask, mask=%par\n", &dma_mask);
		return rc;
	}

	rc = cc_clk_on(new_drvdata);
	if (rc) {
		dev_err(dev, "Failed to enable clock");
		return rc;
	}

	/* Verify correct mapping */
	signature_val = cc_ioread(new_drvdata, CC_REG(HOST_SIGNATURE));
	if (signature_val != CC_DEV_SIGNATURE) {
		dev_err(dev, "Invalid CC signature: SIGNATURE=0x%08X != expected=0x%08X\n",
			signature_val, (u32)CC_DEV_SIGNATURE);
		rc = -EINVAL;
		goto post_clk_err;
	}
	dev_dbg(dev, "CC SIGNATURE=0x%08X\n", signature_val);

	/* Display HW versions */
	dev_info(dev, "ARM CryptoCell %s Driver: HW version 0x%08X, Driver version %s\n",
		 CC_DEV_NAME_STR,
		 cc_ioread(new_drvdata, CC_REG(HOST_VERSION)),
		 DRV_MODULE_VERSION);

	rc = init_cc_regs(new_drvdata, true);
	if (rc) {
		dev_err(dev, "init_cc_regs failed\n");
		goto post_clk_err;
	}

	rc = cc_debugfs_init(new_drvdata);
	if (rc) {
		dev_err(dev, "Failed registering debugfs interface\n");
//.........这里部分代码省略.........

}

struct snd_pcm_ops mxs_pcm_ops = {
	.open		= mxs_pcm_open,
	.close		= mxs_pcm_close,
	.ioctl		= snd_pcm_lib_ioctl,
	.hw_params	= mxs_pcm_hw_params,
	.hw_free	= mxs_pcm_hw_free,
	.prepare	= mxs_pcm_prepare,
	.trigger	= mxs_pcm_trigger,
	.pointer	= mxs_pcm_pointer,
	.copy		= mcs_pcm_copy,
	.mmap		= mxs_pcm_mmap,
};

static u64 mxs_pcm_dma_mask = DMA_BIT_MASK(32);

static int mxs_pcm_new(struct snd_card *card,
			    struct snd_soc_dai *dai, struct snd_pcm *pcm)
{
	size_t size = mxs_pcm_hardware.buffer_bytes_max;

	if (!card->dev->dma_mask)
		card->dev->dma_mask = &mxs_pcm_dma_mask;

	if (!card->dev->coherent_dma_mask)
		card->dev->coherent_dma_mask = DMA_BIT_MASK(32);

	snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, NULL,
					      size, size);

	},
	{
		.start = DMOV_HSUART1_TX_CHAN,
		.end   = DMOV_HSUART1_RX_CHAN,
		.name  = "uartdm_channels",
		.flags = IORESOURCE_DMA,
	},
	{
		.start = DMOV_HSUART1_TX_CRCI,
		.end   = DMOV_HSUART1_RX_CRCI,
		.name  = "uartdm_crci",
		.flags = IORESOURCE_DMA,
	},
};

static u64 msm_uart_dm1_dma_mask = DMA_BIT_MASK(32);

struct platform_device msm_device_uart_dm1 = {
	.name = "msm_serial_hs",
	.id = 0,
	.num_resources = ARRAY_SIZE(msm_uart1_dm_resources),
	.resource = msm_uart1_dm_resources,
	.dev		= {
		.dma_mask = &msm_uart_dm1_dma_mask,
		.coherent_dma_mask = DMA_BIT_MASK(32),
	},
};

static struct resource msm_uart2_dm_resources[] = {
	{
		.start = MSM_UART2DM_PHYS,