本文整理汇总了C++中DISP_REG_SET_FIELD函数的典型用法代码示例。如果您正苦于以下问题:C++ DISP_REG_SET_FIELD函数的具体用法?C++ DISP_REG_SET_FIELD怎么用?C++ DISP_REG_SET_FIELD使用的例子?那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。
在下文中一共展示了DISP_REG_SET_FIELD函数的15个代码示例,这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞,您的评价将有助于系统推荐出更棒的C++代码示例。
示例1: OVLLayerSwitch
int OVLLayerSwitch(unsigned layer, bool en) {
ASSERT(layer<=3);
switch(layer) {
case 0:
DISP_REG_SET_FIELD(SRC_CON_FLD_L0_EN, DISP_REG_OVL_SRC_CON, en);
DISP_REG_SET(DISP_REG_OVL_RDMA0_CTRL, 0);
break;
case 1:
DISP_REG_SET_FIELD(SRC_CON_FLD_L1_EN, DISP_REG_OVL_SRC_CON, en);
DISP_REG_SET(DISP_REG_OVL_RDMA1_CTRL, 0);
break;
case 2:
DISP_REG_SET_FIELD(SRC_CON_FLD_L2_EN, DISP_REG_OVL_SRC_CON, en);
DISP_REG_SET(DISP_REG_OVL_RDMA2_CTRL, 0);
break;
case 3:
DISP_REG_SET_FIELD(SRC_CON_FLD_L3_EN, DISP_REG_OVL_SRC_CON, en);
DISP_REG_SET(DISP_REG_OVL_RDMA3_CTRL, 0);
break;
default:
printk("error: invalid layer=%d \n", layer); // invalid layer
ASSERT(0);
}
return 0;
}
示例2: OVLLayerSwitch
int OVLLayerSwitch(DISP_MODULE_ENUM module,
unsigned layer,
unsigned int en,
void * handle)
{
int idx = ovl_index(module);
ASSERT(layer<=3);
switch(layer) {
case 0:
DISP_REG_SET_FIELD(handle,SRC_CON_FLD_L0_EN, idx*DISP_INDEX_OFFSET+DISP_REG_OVL_SRC_CON, en);
break;
case 1:
DISP_REG_SET_FIELD(handle,SRC_CON_FLD_L1_EN, idx*DISP_INDEX_OFFSET+DISP_REG_OVL_SRC_CON, en);
break;
case 2:
DISP_REG_SET_FIELD(handle,SRC_CON_FLD_L2_EN, idx*DISP_INDEX_OFFSET+DISP_REG_OVL_SRC_CON, en);
break;
case 3:
DISP_REG_SET_FIELD(handle,SRC_CON_FLD_L3_EN, idx*DISP_INDEX_OFFSET+DISP_REG_OVL_SRC_CON, en);
break;
default:
DDPERR("invalid layer=%d\n", layer); // invalid layer
ASSERT(0);
}
return 0;
}
示例3: SCLStart
/* start module */
int SCLStart(void)
{
DISP_REG_SET_FIELD(DSCL_INTEN_FLD_OF_END_INT_EN, DISP_REG_SCL_INTEN, 0);
DISP_REG_SET_FIELD(DSCL_INTEN_FLD_IF_END_INT_EN, DISP_REG_SCL_INTEN, 0);
DISP_REG_SET_FIELD(DSCL_CTRL_FLD_SCL_EN, DISP_REG_SCL_CTRL, 1);
return 0;
}
示例4: rdma_reset
int rdma_reset(DISP_MODULE_ENUM module,void * handle) {
unsigned int delay_cnt=0;
int ret =0;
unsigned int idx = rdma_index(module);
ASSERT(idx <= 2);
DISP_REG_SET_FIELD(handle,GLOBAL_CON_FLD_SOFT_RESET, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_GLOBAL_CON, 1);
while((DISP_REG_GET(idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_GLOBAL_CON)&0x700)==0x100)
{
delay_cnt++;
udelay(10);
if(delay_cnt>10000)
{
ret = -1;
DDPERR("rdma%d_reset timeout, stage 1! DISP_REG_RDMA_GLOBAL_CON=0x%x \n", idx, DISP_REG_GET(idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_GLOBAL_CON));
break;
}
}
DISP_REG_SET_FIELD(handle,GLOBAL_CON_FLD_SOFT_RESET, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_GLOBAL_CON, 0);
delay_cnt =0;
while((DISP_REG_GET(idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_GLOBAL_CON)&0x700)!=0x100)
{
delay_cnt++;
udelay(10);
if(delay_cnt>10000)
{
ret = -1;
DDPERR("rdma%d_reset timeout, stage 2! DISP_REG_RDMA_GLOBAL_CON=0x%x \n", idx, DISP_REG_GET(idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_GLOBAL_CON));
break;
}
}
return ret;
}
示例5: ufoe_reset
static int ufoe_reset(DISP_MODULE_ENUM module, void *handle)
{
DISP_REG_SET_FIELD(handle, START_FLD_DISP_UFO_SW_RST_ENGINE, DISP_REG_UFO_START, 1);
DISP_REG_SET_FIELD(handle, START_FLD_DISP_UFO_SW_RST_ENGINE, DISP_REG_UFO_START, 0);
DDPMSG("ufoe reset done\n");
return 0;
}
示例6: disp_scl_enable_relay_mode
/*
scale reg enable relay mode
*/
void disp_scl_enable_relay_mode(BOOL enable, unsigned src_width, unsigned src_height)
{
DISP_REG_SET_FIELD(DSCL_CFG_FLD_RELAY_MODE, DISP_REG_SCL_CFG, enable);
DISP_REG_SET_FIELD(DSCL_HRZ_SIZE_FLD_HRZ_TARSZ, DISP_REG_SCL_HRZ_SIZE, src_width);
DISP_REG_SET_FIELD(DSCL_HRZ_SIZE_FLD_HRZ_SRCSZ, DISP_REG_SCL_HRZ_SIZE, src_width);
DISP_REG_SET_FIELD(DSCL_VRZ_SIZE_FLD_VRZ_TARSZ, DISP_REG_SCL_VRZ_SIZE, src_height);
DISP_REG_SET_FIELD(DSCL_VRZ_SIZE_FLD_VRZ_SRCSZ, DISP_REG_SCL_VRZ_SIZE, src_height);
}
示例7: disp_scl_reg_enable
/*
scale reg enable
*/
void disp_scl_reg_enable(BOOL enable)
{
BOOL bEnable = enable;
if (bEnable) {
DISP_REG_SET_FIELD(DSCL_INTEN_FLD_OF_END_INT_EN, DISP_REG_SCL_INTEN, 1);
DISP_REG_SET_FIELD(DSCL_INTEN_FLD_IF_END_INT_EN, DISP_REG_SCL_INTEN, 1);
}
DISP_REG_SET_FIELD(DSCL_CTRL_FLD_SCL_EN, DISP_REG_SCL_CTRL, bEnable);
}
示例8: WDMASlowMode
void WDMASlowMode(unsigned int idx,
unsigned int enable,
unsigned int level,
unsigned int cnt,
unsigned int threadhold)
{
DISP_REG_SET_FIELD(WDMA_SMI_CON_FLD_Slow_Enable, DISP_REG_WDMA_SMI_CON, enable&0x01);
DISP_REG_SET_FIELD(WDMA_SMI_CON_FLD_Slow_Count, DISP_REG_WDMA_SMI_CON, cnt&0xff);
DISP_REG_SET_FIELD(WDMA_SMI_CON_FLD_Slow_Level, DISP_REG_WDMA_SMI_CON, level&0x7);
DISP_REG_SET_FIELD(WDMA_SMI_CON_FLD_Threshold, DISP_REG_WDMA_SMI_CON, threadhold&0xf);
}
示例9: SCLConfig
/* configu module */
int SCLConfig(DISP_INTERLACE_FORMAT interlace,
int rotateDegree, int srcWidth, int srcHeight, int dstWidth, int dstHeight, int flip)
{
unsigned char rotate = 0;
unsigned char isInterlace = (interlace == DISP_INTERLACE_FORMAT_NONE) ? 0 : 1;
unsigned char isBottomField = (interlace == DISP_INTERLACE_FORMAT_BOTTOM_FIELD) ? 1 : 0;
switch (rotateDegree) {
case 0:
rotate = 0;
break;
case 90:
rotate = 1;
break;
case 180:
rotate = 2;
break;
case 270:
rotate = 3;
break;
default:
DDP_SCL_LOG("unsupport rotate degree %d", rotateDegree);
break;
}
DDP_SCL_LOG("DpEngine_SCL config...\n");
DDP_SCL_LOG(" input (w, h) : %d %d\n", srcWidth, srcHeight);
DDP_SCL_LOG(" output (w, h) : %d %d\n", dstWidth, dstHeight);
DDP_SCL_LOG(" rotate : %d, flip=%d\n", rotate, flip);
disp_scl_set_scale_param(srcWidth,
srcHeight,
dstWidth,
dstHeight,
isInterlace, /* 0=progressive source, 1=interlaced source */
isBottomField, /* 0=source is top field, 1=source is bottom field */
rotate, /* source rotated; 0=no, 1=90, 2=180, 3=270 (clockwise) */
flip); /* source horizontal flipped; 0=no flip, 1=flipped */
DISP_REG_SET_FIELD(DSCL_INP_CHKSUM_FLD_INP_CHKSUM_EN, DISP_REG_SCL_INP_CHKSUM, 1);
DISP_REG_SET_FIELD(DSCL_OUTP_CHKSUM_FLD_OUTP_CHKSUM_EN, DISP_REG_SCL_OUTP_CHKSUM, 1);
return 0;
}
示例10: ovl_start
int ovl_start(DISP_MODULE_ENUM module, void *handle)
{
int idx = ovl_index(module);
int idx_offset = idx*DISP_OVL_INDEX_OFFSET;
DISP_REG_SET(handle, idx_offset+DISP_REG_OVL_EN, 0x01);
int enable_ovl_irq = 1;
#if defined(CONFIG_TRUSTONIC_TEE_SUPPORT) && defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT)
enable_ovl_irq = 1;
#else
if(gEnableIRQ==1)
enable_ovl_irq = 1;
else
enable_ovl_irq = 0;
#endif
if(enable_ovl_irq)
DISP_REG_SET(handle, idx_offset+DISP_REG_OVL_INTEN, 0x1e2);
else
DISP_REG_SET(handle, idx_offset+DISP_REG_OVL_INTEN, 0x1e0);
DISP_REG_SET_FIELD(handle, DATAPATH_CON_FLD_LAYER_SMI_ID_EN,
idx_offset+DISP_REG_OVL_DATAPATH_CON, 0x1);
return 0;
}
示例11: SCLStop
/* stop module */
int SCLStop(void)
{
DISP_REG_SET_FIELD(DSCL_CTRL_FLD_SCL_EN, DISP_REG_SCL_CTRL, 0);
DISP_REG_SET(DISP_REG_SCL_INTEN, 0);
DISP_REG_SET(DISP_REG_SCL_INTSTA, 0);
return 0;
}
示例12: RDMAReset
int RDMAReset(unsigned idx)
{
unsigned int delay_cnt = 0;
/* static unsigned int cnt=0; */
ASSERT(idx <= 2);
DISP_REG_SET_FIELD(GLOBAL_CON_FLD_SOFT_RESET,
idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_GLOBAL_CON, 1);
while ((DISP_REG_GET(idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_GLOBAL_CON) & 0x700) == 0x100) {
delay_cnt++;
if (delay_cnt > 10000) {
DISP_ERR
("[DDP] error, RDMAReset(%d) timeout, stage 1! DISP_REG_RDMA_GLOBAL_CON=0x%x\n",
idx, DISP_REG_GET(idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_GLOBAL_CON));
break;
}
}
DISP_REG_SET_FIELD(GLOBAL_CON_FLD_SOFT_RESET,
idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_GLOBAL_CON, 0);
while ((DISP_REG_GET(idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_GLOBAL_CON) & 0x700) != 0x100) {
delay_cnt++;
if (delay_cnt > 10000) {
DISP_ERR
("[DDP] error, RDMAReset(%d) timeout, stage 2! DISP_REG_RDMA_GLOBAL_CON=0x%x\n",
idx, DISP_REG_GET(idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_GLOBAL_CON));
ddp_dump_info(DISP_MODULE_CONFIG);
ddp_dump_info(DISP_MODULE_MUTEX);
ddp_dump_info(DISP_MODULE_OVL);
ddp_dump_info(DISP_MODULE_RDMA);
break;
}
}
#if 0
DISP_REG_SET(idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_GLOBAL_CON, 0x00);
DISP_REG_SET(idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_SIZE_CON_0, 0x00);
DISP_REG_SET(idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_SIZE_CON_1, 0x00);
DISP_REG_SET(idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_MEM_CON, 0x00);
DISP_REG_SET(idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_MEM_START_ADDR, 0x00);
DISP_REG_SET(idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_MEM_SRC_PITCH, 0x00);
DISP_REG_SET(idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_MEM_GMC_SETTING_1, 0x20); /* /TODO: need check */
/* DISP_REG_SET(idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_FIFO_CON , 0x80f00008); ///TODO: need check */
#endif
return 0;
}
示例13: hdmi_dst_display_path_config
int hdmi_dst_display_path_config(bool enable)
{
HDMI_FUNC();
if (enable)
{
//FIXME: now nothing can be seen on TV if output UYVY from WDMA0
unsigned int hdmiSourceAddr = hdmi_mva_r;// + p->hdmi_width * p->hdmi_height * hdmi_bpp * hdmi_buffer_read_id;
struct disp_path_config_struct config = {0};
// Config RDMA->DPI1
config.srcWidth = 1280;
config.srcHeight = 720;
config.srcModule = DISP_MODULE_RDMA1;
config.inFormat = RDMA_INPUT_FORMAT_ARGB;
config.outFormat = RDMA_OUTPUT_FORMAT_ARGB;
config.addr = hdmiSourceAddr;
config.pitch = config.srcWidth * 4;
config.dstModule = DISP_MODULE_DPI0;
//if(-1 == dp_mutex_dst)
// dp_mutex_dst = disp_lock_mutex();
dp_mutex_dst = 2;
disp_dump_reg(DISP_MODULE_RDMA0);
disp_dump_reg(DISP_MODULE_RDMA1);
disp_dump_reg(DISP_MODULE_CONFIG);
HDMI_LOG("Get mutex ID %d for RDMA1>DPI1\n", dp_mutex_dst);
disp_path_get_mutex_(dp_mutex_dst);
disp_path_config_(&config, dp_mutex_dst);
disp_path_release_mutex_(dp_mutex_dst);
disp_dump_reg(DISP_MODULE_CONFIG);
disp_dump_reg(DISP_MODULE_RDMA0);
disp_dump_reg(DISP_MODULE_RDMA1);
}
else
{
if (-1 != dp_mutex_dst)
{
//FIXME: release mutex timeout
HDMI_LOG("Stop RDMA1>DPI1\n");
disp_path_get_mutex_(dp_mutex_dst);
DISP_REG_SET_FIELD(1 << dp_mutex_src , DISP_REG_CONFIG_MUTEX_INTEN, 1);
RDMAStop(1);
RDMAReset(1);
disp_path_release_mutex_(dp_mutex_dst);
//disp_unlock_mutex(dp_mutex_dst);
dp_mutex_dst = -1;
}
}
return 0;
}
示例14: RDMAReset
int RDMAReset(unsigned idx) {
unsigned int delay_cnt = 0;
ASSERT(idx <= 2);
DISP_REG_SET_FIELD(GLOBAL_CON_FLD_SOFT_RESET, idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_GLOBAL_CON, 1);
while((DISP_REG_GET(idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_GLOBAL_CON)&0x700)==0x100) {
delay_cnt++;
if(delay_cnt > 10000) {
printf("[DDP] error, RDMAReset(%d) timeout, stage 1! DISP_REG_RDMA_GLOBAL_CON=0x%x \n", idx, DISP_REG_GET(idx * 0x1000 + DISP_REG_RDMA_GLOBAL_CON));
break;
}
}
DISP_REG_SET_FIELD(GLOBAL_CON_FLD_SOFT_RESET, idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_GLOBAL_CON, 0);
return 0;
}
示例15: RDMAStop
int RDMAStop(unsigned idx) {
ASSERT(idx <= 2);
DISP_REG_SET_FIELD(GLOBAL_CON_FLD_ENGINE_EN, idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_GLOBAL_CON, 0);
DISP_REG_SET(idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_INT_ENABLE, 0);
DISP_REG_SET(idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_INT_STATUS, 0);
return 0;
}