C++ CyIntSetVector函数代码示例

/*******************************************************************************
* Function Name: SPIM_Init
********************************************************************************
*
* Summary:
*  Inits/Restores default SPIM configuration provided with customizer.
*
* Parameters:
*  None.
*
* Return:
*  None.
*
* Side Effects:
*  When this function is called it initializes all of the necessary parameters
*  for execution. i.e. setting the initial interrupt mask, configuring the 
*  interrupt service routine, configuring the bit-counter parameters and 
*  clearing the FIFO and Status Register.
*
* Reentrant:
*  No.
*
*******************************************************************************/
void SPIM_Init(void)
{    
    /* Initialize the Bit counter */
    SPIM_COUNTER_PERIOD_REG = SPIM_BITCTR_INIT;
    
    /* ISR initialization  */  
    #if(SPIM_InternalTxInterruptEnabled)
    
        CyIntDisable(SPIM_TX_ISR_NUMBER);

        /* Set the ISR to point to the SPIM_isr Interrupt. */
        CyIntSetVector(SPIM_TX_ISR_NUMBER, SPIM_TX_ISR);

        /* Set the priority. */
        CyIntSetPriority(SPIM_TX_ISR_NUMBER, SPIM_TX_ISR_PRIORITY);
        
    #endif /* SPIM_InternalTxInterruptEnabled */                                
    
    #if(SPIM_InternalRxInterruptEnabled)
    
        CyIntDisable(SPIM_RX_ISR_NUMBER);

        /* Set the ISR to point to the SPIM_isr Interrupt. */
        CyIntSetVector(SPIM_RX_ISR_NUMBER, SPIM_RX_ISR);

        /* Set the priority. */
        CyIntSetPriority(SPIM_RX_ISR_NUMBER, SPIM_RX_ISR_PRIORITY);
        
    #endif /* SPIM_InternalRxInterruptEnabled */
    
    /* Clear any stray data from the RX and TX FIFO */    
	SPIM_ClearFIFO();
	
	#if(SPIM_RXBUFFERSIZE > 4u)
    
        SPIM_rxBufferRead = 0u;
        SPIM_rxBufferWrite = 0u;

    #endif /* SPIM_RXBUFFERSIZE > 4u */
	
    #if(SPIM_TXBUFFERSIZE > 4u)
    
        SPIM_txBufferRead = 0u;
        SPIM_txBufferWrite = 0u;

    #endif /* SPIM_TXBUFFERSIZE > 4u */
    
    (void) SPIM_ReadTxStatus(); /* Clear any pending status bits */
    (void) SPIM_ReadRxStatus(); /* Clear any pending status bits */
	
	/* Configure the Initial interrupt mask */
    #if (SPIM_TXBUFFERSIZE > 4u)
        SPIM_TX_STATUS_MASK_REG  = SPIM_TX_INIT_INTERRUPTS_MASK & 
                                                ~SPIM_STS_TX_FIFO_NOT_FULL;                    
	#else /* SPIM_TXBUFFERSIZE < 4u */    
        SPIM_TX_STATUS_MASK_REG  = SPIM_TX_INIT_INTERRUPTS_MASK;       
	#endif /* SPIM_TXBUFFERSIZE > 4u */
    
    SPIM_RX_STATUS_MASK_REG  = SPIM_RX_INIT_INTERRUPTS_MASK; 
}

    /*******************************************************************************
    * Function Name: SCB_1_UartInit
    ****************************************************************************//**
    *
    *  Configures the SCB for the UART operation.
    *
    *******************************************************************************/
    void SCB_1_UartInit(void)
    {
        /* Configure UART interface */
        SCB_1_CTRL_REG = SCB_1_UART_DEFAULT_CTRL;

        /* Configure sub-mode: UART, SmartCard or IrDA */
        SCB_1_UART_CTRL_REG = SCB_1_UART_DEFAULT_UART_CTRL;

        /* Configure RX direction */
        SCB_1_UART_RX_CTRL_REG = SCB_1_UART_DEFAULT_UART_RX_CTRL;
        SCB_1_RX_CTRL_REG      = SCB_1_UART_DEFAULT_RX_CTRL;
        SCB_1_RX_FIFO_CTRL_REG = SCB_1_UART_DEFAULT_RX_FIFO_CTRL;
        SCB_1_RX_MATCH_REG     = SCB_1_UART_DEFAULT_RX_MATCH_REG;

        /* Configure TX direction */
        SCB_1_UART_TX_CTRL_REG = SCB_1_UART_DEFAULT_UART_TX_CTRL;
        SCB_1_TX_CTRL_REG      = SCB_1_UART_DEFAULT_TX_CTRL;
        SCB_1_TX_FIFO_CTRL_REG = SCB_1_UART_DEFAULT_TX_FIFO_CTRL;

    #if !(SCB_1_CY_SCBIP_V0 || SCB_1_CY_SCBIP_V1)
        SCB_1_UART_FLOW_CTRL_REG = SCB_1_UART_DEFAULT_FLOW_CTRL;
    #endif /* !(SCB_1_CY_SCBIP_V0 || SCB_1_CY_SCBIP_V1) */

        /* Configure interrupt with UART handler but do not enable it */
    #if(SCB_1_SCB_IRQ_INTERNAL)
        CyIntDisable    (SCB_1_ISR_NUMBER);
        CyIntSetPriority(SCB_1_ISR_NUMBER, SCB_1_ISR_PRIORITY);
        (void) CyIntSetVector(SCB_1_ISR_NUMBER, &SCB_1_SPI_UART_ISR);
    #endif /* (SCB_1_SCB_IRQ_INTERNAL) */

        /* Configure WAKE interrupt */
    #if(SCB_1_UART_RX_WAKEUP_IRQ)
        CyIntDisable    (SCB_1_RX_WAKE_ISR_NUMBER);
        CyIntSetPriority(SCB_1_RX_WAKE_ISR_NUMBER, SCB_1_RX_WAKE_ISR_PRIORITY);
        (void) CyIntSetVector(SCB_1_RX_WAKE_ISR_NUMBER, &SCB_1_UART_WAKEUP_ISR);
    #endif /* (SCB_1_UART_RX_WAKEUP_IRQ) */

        /* Configure interrupt sources */
        SCB_1_INTR_I2C_EC_MASK_REG = SCB_1_UART_DEFAULT_INTR_I2C_EC_MASK;
        SCB_1_INTR_SPI_EC_MASK_REG = SCB_1_UART_DEFAULT_INTR_SPI_EC_MASK;
        SCB_1_INTR_SLAVE_MASK_REG  = SCB_1_UART_DEFAULT_INTR_SLAVE_MASK;
        SCB_1_INTR_MASTER_MASK_REG = SCB_1_UART_DEFAULT_INTR_MASTER_MASK;
        SCB_1_INTR_RX_MASK_REG     = SCB_1_UART_DEFAULT_INTR_RX_MASK;
        SCB_1_INTR_TX_MASK_REG     = SCB_1_UART_DEFAULT_INTR_TX_MASK;
    
        /* Configure TX interrupt sources to restore. */
        SCB_1_IntrTxMask = LO16(SCB_1_INTR_TX_MASK_REG);

    #if(SCB_1_INTERNAL_RX_SW_BUFFER_CONST)
        SCB_1_rxBufferHead     = 0u;
        SCB_1_rxBufferTail     = 0u;
        SCB_1_rxBufferOverflow = 0u;
    #endif /* (SCB_1_INTERNAL_RX_SW_BUFFER_CONST) */

    #if(SCB_1_INTERNAL_TX_SW_BUFFER_CONST)
        SCB_1_txBufferHead = 0u;
        SCB_1_txBufferTail = 0u;
    #endif /* (SCB_1_INTERNAL_TX_SW_BUFFER_CONST) */
    }

    /*******************************************************************************
    * Function Name: UART_BCP_UartInit
    ********************************************************************************
    *
    * Summary:
    *  Configures the SCB for the UART operation.
    *
    * Parameters:
    *  None
    *
    * Return:
    *  None
    *
    *******************************************************************************/
    void UART_BCP_UartInit(void)
    {
        /* Configure UART interface */
        UART_BCP_CTRL_REG = UART_BCP_UART_DEFAULT_CTRL;

        /* Configure sub-mode: UART, SmartCard or IrDA */
        UART_BCP_UART_CTRL_REG = UART_BCP_UART_DEFAULT_UART_CTRL;

        /* Configure RX direction */
        UART_BCP_UART_RX_CTRL_REG = UART_BCP_UART_DEFAULT_UART_RX_CTRL;
        UART_BCP_RX_CTRL_REG      = UART_BCP_UART_DEFAULT_RX_CTRL;
        UART_BCP_RX_FIFO_CTRL_REG = UART_BCP_UART_DEFAULT_RX_FIFO_CTRL;
        UART_BCP_RX_MATCH_REG     = UART_BCP_UART_DEFAULT_RX_MATCH_REG;

        /* Configure TX direction */
        UART_BCP_UART_TX_CTRL_REG = UART_BCP_UART_DEFAULT_UART_TX_CTRL;
        UART_BCP_TX_CTRL_REG      = UART_BCP_UART_DEFAULT_TX_CTRL;
        UART_BCP_TX_FIFO_CTRL_REG = UART_BCP_UART_DEFAULT_TX_FIFO_CTRL;

    #if !(UART_BCP_CY_SCBIP_V0 || UART_BCP_CY_SCBIP_V1)
        UART_BCP_UART_FLOW_CTRL_REG = UART_BCP_UART_DEFAULT_FLOW_CTRL;
    #endif /* !(UART_BCP_CY_SCBIP_V0 || UART_BCP_CY_SCBIP_V1) */

        /* Configure interrupt with UART handler but do not enable it */
    #if(UART_BCP_SCB_IRQ_INTERNAL)
        CyIntDisable    (UART_BCP_ISR_NUMBER);
        CyIntSetPriority(UART_BCP_ISR_NUMBER, UART_BCP_ISR_PRIORITY);
        (void) CyIntSetVector(UART_BCP_ISR_NUMBER, &UART_BCP_SPI_UART_ISR);
    #endif /* (UART_BCP_SCB_IRQ_INTERNAL) */

        /* Configure WAKE interrupt */
    #if(UART_BCP_UART_RX_WAKEUP_IRQ)
        CyIntDisable    (UART_BCP_RX_WAKE_ISR_NUMBER);
        CyIntSetPriority(UART_BCP_RX_WAKE_ISR_NUMBER, UART_BCP_RX_WAKE_ISR_PRIORITY);
        (void) CyIntSetVector(UART_BCP_RX_WAKE_ISR_NUMBER, &UART_BCP_UART_WAKEUP_ISR);
    #endif /* (UART_BCP_UART_RX_WAKEUP_IRQ) */

        /* Configure interrupt sources */
        UART_BCP_INTR_I2C_EC_MASK_REG = UART_BCP_UART_DEFAULT_INTR_I2C_EC_MASK;
        UART_BCP_INTR_SPI_EC_MASK_REG = UART_BCP_UART_DEFAULT_INTR_SPI_EC_MASK;
        UART_BCP_INTR_SLAVE_MASK_REG  = UART_BCP_UART_DEFAULT_INTR_SLAVE_MASK;
        UART_BCP_INTR_MASTER_MASK_REG = UART_BCP_UART_DEFAULT_INTR_MASTER_MASK;
        UART_BCP_INTR_RX_MASK_REG     = UART_BCP_UART_DEFAULT_INTR_RX_MASK;
        UART_BCP_INTR_TX_MASK_REG     = UART_BCP_UART_DEFAULT_INTR_TX_MASK;

    #if(UART_BCP_INTERNAL_RX_SW_BUFFER_CONST)
        UART_BCP_rxBufferHead     = 0u;
        UART_BCP_rxBufferTail     = 0u;
        UART_BCP_rxBufferOverflow = 0u;
    #endif /* (UART_BCP_INTERNAL_RX_SW_BUFFER_CONST) */

    #if(UART_BCP_INTERNAL_TX_SW_BUFFER_CONST)
        UART_BCP_txBufferHead = 0u;
        UART_BCP_txBufferTail = 0u;
    #endif /* (UART_BCP_INTERNAL_TX_SW_BUFFER_CONST) */
    }

CY_CFG_SECTION
static void ClockSetup(void)
{
	/* Enable HALF_EN before trimming for the flash accelerator. */
	CY_SET_REG32((void CYXDATA *)(CYREG_CLK_SELECT), (CY_GET_REG32((void *)CYREG_CLK_SELECT) | 0x00040000u));

	/* Setup and trim IMO based on desired frequency. */
	CySysClkWriteImoFreq(24u);

	/* Disable HALF_EN since it is not required at this IMO frequency. */
	CY_SET_REG32((void CYXDATA *)(CYREG_CLK_SELECT), (CY_GET_REG32((void *)CYREG_CLK_SELECT) & 0xFFFBFFFFu));
	/* CYDEV_CLK_ILO_CONFIG Starting address: CYDEV_CLK_ILO_CONFIG */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_ILO_CONFIG), 0x80000006u);


	/* CYDEV_CLK_SELECT00 Starting address: CYDEV_CLK_SELECT00 */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT03), 0x00000020u);
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT08), 0x00000010u);

	/* CYDEV_CLK_IMO_CONFIG Starting address: CYDEV_CLK_IMO_CONFIG */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_IMO_CONFIG), 0x80000000u);

	/* CYDEV_CLK_DIVIDER_A00 Starting address: CYDEV_CLK_DIVIDER_A00 */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_DIVIDER_A00), 0x80000001u);

	/* CYDEV_CLK_DIVIDER_B00 Starting address: CYDEV_CLK_DIVIDER_B00 */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_DIVIDER_B00), 0x800000CFu);

	(void)CyIntSetVector(9u, &CySysWdtIsr);
	CyIntEnable(9u);
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONFIG), 0x00000000u);
}

/*****************************************************************************
* Function Name: _Watchdog_Init()
******************************************************************************
* Summary:
*   Initialize the watchdog.
*
* Parameters:
*   None.
*
* Return:
*   None.
*
* Note:
*
*****************************************************************************/
void _Watchdog_Init(void)
{
    // Unlock the WDT registers for modification.
	CySysWdtUnlock();
    
    // Write Mode for Counters as Interrupt on Match.
    CySysWdtWriteMode(CY_SYS_WDT_COUNTER0, CY_SYS_WDT_MODE_INT);
    CySysWdtWriteMode(CY_SYS_WDT_COUNTER1, CY_SYS_WDT_MODE_INT);
    
    // Set Clear on Match for Counters.
	CySysWdtWriteClearOnMatch(CY_SYS_WDT_COUNTER0, TRUE);
    CySysWdtWriteClearOnMatch(CY_SYS_WDT_COUNTER1, TRUE);
    
    // Set Watchdog interrupt to lower priority.
	CyIntSetPriority(WATCHDOG_INT_VEC_NUM, WATCHDOG_INT_VEC_PRIORITY);
    
    // Enable Watchdog Interrupt using Interrupt number.
    CyIntEnable(WATCHDOG_INT_VEC_NUM);
    
    // Write the match value in Counters.
	CySysWdtWriteMatch(CY_SYS_WDT_COUNTER0, WATCHDOG_COUNTER0_PERIOD);
    CySysWdtWriteMatch(CY_SYS_WDT_COUNTER1, WATCHDOG_COUNTER1_PERIOD);
    
    // Enable Counters.
    CySysWdtEnable(CY_SYS_WDT_COUNTER0_MASK);
    CySysWdtEnable(CY_SYS_WDT_COUNTER1_MASK);
	
	// Lock Watchdog to prevent further changes.
    CySysWdtLock();
    
    // Set the Watchdog Interrupt vector to the address of Interrupt routine 
	// _Watchdog_Handler.
	CyIntSetVector(WATCHDOG_INT_VEC_NUM, &_Watchdog_Handler);
}

/*******************************************************************************
* Function Name: EzI2C_SaveConfig
********************************************************************************
*
* Summary:
*  The Enable wakeup from Sleep Mode selection influences this function
*  implementation:
*   Unchecked: Stores the component non-retention configuration registers.
*   Checked:   Enables backup regulator of the I2C hardware. If a transaction
*              intended for component executes during this function call,
*              it waits until the current transaction is completed and
*              I2C hardware is ready to go to sleep mode. All subsequent
*              I2C traffic is NAKed until the device is put to sleep mode.
*
* Parameters:
*  None.
*
* Return:
*  None.
*
* Global variables:
*  EzI2C_backup - The non-retention registers are saved to.
*
* Reentrant:
*  No.
*
*******************************************************************************/
void EzI2C_SaveConfig(void) 
{
#if (EzI2C_WAKEUP_ENABLED)
    uint8 interruptState;
#endif /* (EzI2C_WAKEUP_ENABLED) */

    /* Store component configuration into backup structure */
    EzI2C_backup.cfg     = EzI2C_CFG_REG;
    EzI2C_backup.xcfg    = EzI2C_XCFG_REG;
    EzI2C_backup.adr     = EzI2C_ADDR_REG;
    EzI2C_backup.clkDiv1 = EzI2C_CLKDIV1_REG;
    EzI2C_backup.clkDiv2 = EzI2C_CLKDIV2_REG;

#if (EzI2C_WAKEUP_ENABLED)
    /* Enable I2C backup regulator */
    interruptState = CyEnterCriticalSection();
    EzI2C_PWRSYS_CR1_REG |= EzI2C_PWRSYS_CR1_I2C_BACKUP;
    CyExitCriticalSection(interruptState);

    /* Wait for completion of the current transaction. The following
    * transactions have to be NACKed until the device enters the low power mode.
    * After a wakeup, the force NACK bit is cleared automatically.
    */
    EzI2C_XCFG_REG |= EzI2C_XCFG_FORCE_NACK;
    while (0u == (EzI2C_XCFG_REG & EzI2C_XCFG_SLEEP_READY))
    {
    }

     /* Setup wakeup interrupt */
    EzI2C_DisableInt();
    EzI2C_wakeupSource = 0u; /* Clear wakeup event */
    (void) CyIntSetVector(EzI2C_ISR_NUMBER, &EzI2C_WAKEUP_ISR);
    EzI2C_EnableInt();
#endif /* (EzI2C_WAKEUP_ENABLED) */
}

CY_CFG_SECTION
static void ClockSetup(void)
{

	/* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */
	CY_SET_REG32((void CYXDATA *)(CYREG_CPUSS_FLASH_CTL), (0x0012u));
	/* Setup and trim IMO based on desired frequency. */
	CySysClkWriteImoFreq(48u);
	/* CYDEV_CLK_ILO_CONFIG Starting address: CYDEV_CLK_ILO_CONFIG */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_ILO_CONFIG), 0x80000006u);


	/* Setup phase aligned clocks */
	CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL0, 0x00002200u);
	CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF40u);
	CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL1, 0x00002200u);
	CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF41u);

	/* CYDEV_CLK_IMO_CONFIG Starting address: CYDEV_CLK_IMO_CONFIG */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_IMO_CONFIG), 0x80000000u);

	/* CYDEV_CLK_SELECT Starting address: CYDEV_CLK_SELECT */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT), 0x00040000u);

	/* CYDEV_PERI_PCLK_CTL5 Starting address: CYDEV_PERI_PCLK_CTL5 */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL5), 0x00000040u);

	/* CYDEV_PERI_PCLK_CTL3 Starting address: CYDEV_PERI_PCLK_CTL3 */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL3), 0x00000041u);

	(void)CyIntSetVector(7u, &CySysWdtIsr);
	CyIntEnable(7u);
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONFIG), 0x00000000u);
}

CY_CFG_SECTION
static void ClockSetup(void)
{

	/* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */
	CY_SET_REG32((void CYXDATA *)(CYREG_CPUSS_FLASH_CTL), (0x0012u));

	/* Start the WCO */
	CySysClkWcoStart();
	CyDelayCycles(12000000u); /* WCO may take up to 500ms to start */
	(void)CySysClkWcoSetPowerMode(CY_SYS_CLK_WCO_LPM);    /* Switch to the low power mode */

	/* Setup and trim IMO based on desired frequency. */
	CySysClkWriteImoFreq(48u);
	/* CYDEV_CLK_ILO_CONFIG Starting address: CYDEV_CLK_ILO_CONFIG */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_ILO_CONFIG), 0x80000006u);

	/* CYDEV_WDT_CONFIG Starting address: CYDEV_WDT_CONFIG */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONFIG), 0x40000000u);


	/* Enable fast start mode for XO */
	CY_SET_REG32((void*)CYREG_BLE_BLERD_BB_XO, CY_GET_REG32((void*)CYREG_BLE_BLERD_BB_XO) | (uint32)0x02u);
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_BLE_BLERD_BB_XO_CAPTRIM), 0x00003E2Du);
	/*Set XTAL(ECO) divider*/
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_BLE_BLESS_XTAL_CLK_DIV_CONFIG), 0x00000000u);
	/* Disable Crystal Stable Interrupt before enabling ECO */
	CY_SET_REG32((void*)CYREG_BLE_BLESS_LL_DSM_CTRL, CY_GET_REG32((void*)CYREG_BLE_BLESS_LL_DSM_CTRL) & (~(uint32)0x08u));
	/* Start the ECO and do not check status since it is not needed for HFCLK */
	(void)CySysClkEcoStart(2000u);
	CyDelayUs(1500u); /* Wait to stabalize */

	/* Setup phase aligned clocks */
	CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL1, 0x00BB7F00u);
	CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF41u);
	CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL0, 0x0001A000u);
	CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF40u);

	/* CYDEV_CLK_IMO_CONFIG Starting address: CYDEV_CLK_IMO_CONFIG */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_IMO_CONFIG), 0x80000000u);

	/* CYDEV_CLK_SELECT Starting address: CYDEV_CLK_SELECT */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT), 0x00040000u);

	/* CYDEV_PERI_PCLK_CTL7 Starting address: CYDEV_PERI_PCLK_CTL7 */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL7), 0x00000041u);

	/* CYDEV_PERI_PCLK_CTL2 Starting address: CYDEV_PERI_PCLK_CTL2 */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL2), 0x00000040u);

	(void)CyIntSetVector(8u, &CySysWdtIsr);
	CyIntEnable(8u);
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_MATCH), 0x00000020u);
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONFIG), 0x40000005u);
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONTROL), 0x00000008u);
	while ((CY_GET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONTROL)) & 0x00000008u) != 0u) { }
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONTROL), 0x00000001u);
}

    /*******************************************************************************
    * Function Name: I2C_1_I2CInit
    ********************************************************************************
    *
    * Summary:
    *  Configures the SCB for the I2C operation.
    *
    * Parameters:
    *  None
    *
    * Return:
    *  None
    *
    *******************************************************************************/
    void I2C_1_I2CInit(void)
    {
        /* Configure I2C interface */
        I2C_1_CTRL_REG     = I2C_1_I2C_DEFAULT_CTRL;
        I2C_1_I2C_CTRL_REG = I2C_1_I2C_DEFAULT_I2C_CTRL;

    #if(I2C_1_CY_SCBIP_V0)
        /* Adjust SDA filter settings. Ticket ID#150521 */
        I2C_1_SET_I2C_CFG_SDA_FILT_TRIM(I2C_1_EC_AM_I2C_CFG_SDA_FILT_TRIM);
    #endif /* (I2C_1_CY_SCBIP_V0) */

        /* Configure RX direction */
        I2C_1_RX_CTRL_REG      = I2C_1_I2C_DEFAULT_RX_CTRL;
        I2C_1_RX_FIFO_CTRL_REG = I2C_1_I2C_DEFAULT_RX_FIFO_CTRL;

        /* Set default address and mask */
        I2C_1_RX_MATCH_REG     = I2C_1_I2C_DEFAULT_RX_MATCH;

        /* Configure TX direction */
        I2C_1_TX_CTRL_REG      = I2C_1_I2C_DEFAULT_TX_CTRL;
        I2C_1_TX_FIFO_CTRL_REG = I2C_1_I2C_DEFAULT_TX_FIFO_CTRL;

        /* Configure interrupt with I2C handler but do not enable it */
        CyIntDisable    (I2C_1_ISR_NUMBER);
        CyIntSetPriority(I2C_1_ISR_NUMBER, I2C_1_ISR_PRIORITY);
    #if(!I2C_1_I2C_EXTERN_INTR_HANDLER)
        (void) CyIntSetVector(I2C_1_ISR_NUMBER, &I2C_1_I2C_ISR);
    #endif /* (I2C_1_I2C_EXTERN_INTR_HANDLER) */

        /* Configure interrupt sources */
    #if(!I2C_1_CY_SCBIP_V1_I2C_ONLY)
        I2C_1_INTR_SPI_EC_MASK_REG = I2C_1_I2C_DEFAULT_INTR_SPI_EC_MASK;
    #endif /* (!I2C_1_CY_SCBIP_V1_I2C_ONLY) */

        I2C_1_INTR_I2C_EC_MASK_REG = I2C_1_I2C_DEFAULT_INTR_I2C_EC_MASK;
        I2C_1_INTR_SLAVE_MASK_REG  = I2C_1_I2C_DEFAULT_INTR_SLAVE_MASK;
        I2C_1_INTR_MASTER_MASK_REG = I2C_1_I2C_DEFAULT_INTR_MASTER_MASK;
        I2C_1_INTR_RX_MASK_REG     = I2C_1_I2C_DEFAULT_INTR_RX_MASK;
        I2C_1_INTR_TX_MASK_REG     = I2C_1_I2C_DEFAULT_INTR_TX_MASK;

        /* Configure global variables */
        I2C_1_state = I2C_1_I2C_FSM_IDLE;

    #if(I2C_1_I2C_SLAVE)
        /* Internal slave variable */
        I2C_1_slStatus        = 0u;
        I2C_1_slRdBufIndex    = 0u;
        I2C_1_slWrBufIndex    = 0u;
        I2C_1_slOverFlowCount = 0u;
    #endif /* (I2C_1_I2C_SLAVE) */

    #if(I2C_1_I2C_MASTER)
    /* Internal master variable */
        I2C_1_mstrStatus     = 0u;
        I2C_1_mstrRdBufIndex = 0u;
        I2C_1_mstrWrBufIndex = 0u;
    #endif /* (I2C_1_I2C_MASTER) */
    }

CY_CFG_SECTION
static void ClockSetup(void)
{

	/* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */
	CY_SET_REG32((void CYXDATA *)(CYREG_CPUSS_FLASH_CTL), (0x0012u));

	/* Start the WCO */
	CySysClkWcoStart();
	(void)CySysClkWcoSetPowerMode(CY_SYS_CLK_WCO_LPM);    /* Switch to the low power mode */

	/* Setup and trim IMO based on desired frequency. */
	CySysClkWriteImoFreq(24u);
	/* CYDEV_CLK_ILO_CONFIG Starting address: CYDEV_CLK_ILO_CONFIG */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_ILO_CONFIG), 0x80000006u);


	/* Enable fast start mode for XO */
	CY_SET_REG32((void*)CYREG_BLE_BLERD_BB_XO, CY_GET_REG32((void*)CYREG_BLE_BLERD_BB_XO) | (uint32)0x02u);
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_BLE_BLERD_BB_XO_CAPTRIM), 0x00003E2Du);
	/* Disable Crystal Stable Interrupt before enabling ECO */
	CY_SET_REG32((void*)CYREG_BLE_BLESS_LL_DSM_CTRL, CY_GET_REG32((void*)CYREG_BLE_BLESS_LL_DSM_CTRL) & (~(uint32)0x08u));
	/* Start the ECO and do not check status since it is not needed for HFCLK */
	(void)CySysClkEcoStart(2000u);
	CyDelayUs(1500u); /* Wait to stabalize */

	/* Setup phase aligned clocks */
	CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL2, 0x0001DF00u);
	CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF42u);
	CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL0, 0x00000E00u);
	CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF40u);
	CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL1, 0x00001000u);
	CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF41u);

	/* CYDEV_CLK_IMO_CONFIG Starting address: CYDEV_CLK_IMO_CONFIG */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_IMO_CONFIG), 0x80000000u);

	/* CYDEV_PERI_PCLK_CTL11 Starting address: CYDEV_PERI_PCLK_CTL11 */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL11), 0x00000042u);

	/* CYDEV_PERI_PCLK_CTL8 Starting address: CYDEV_PERI_PCLK_CTL8 */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL8), 0x00000042u);

	/* CYDEV_PERI_PCLK_CTL7 Starting address: CYDEV_PERI_PCLK_CTL7 */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL7), 0x00000042u);

	/* CYDEV_PERI_PCLK_CTL2 Starting address: CYDEV_PERI_PCLK_CTL2 */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL2), 0x00000040u);

	/* CYDEV_PERI_PCLK_CTL1 Starting address: CYDEV_PERI_PCLK_CTL1 */
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL1), 0x00000041u);

	(void)CyIntSetVector(8u, &CySysWdtIsr);
	CyIntEnable(8u);
	CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONFIG), 0x00000000u);
	/* Set Flash Cycles based on newly configured 24.00MHz HFCLK. */
	CY_SET_REG32((void CYXDATA *)(CYREG_CPUSS_FLASH_CTL), (0x0011u));
}

/*******************************************************************************
* Function Name: USBUART_Suspend
********************************************************************************
*
* Summary:
*  This function disables the USBFS block and prepares for power down mode.
*
* Parameters:
*  None.
*
* Return:
*   None.
*
* Global variables:
*  USBUART_backup.enable:  modified.
*
* Reentrant:
*  No.
*
*******************************************************************************/
void USBUART_Suspend(void) 
{
    uint8 enableInterrupts;
    enableInterrupts = CyEnterCriticalSection();

    if((CY_GET_REG8(USBUART_CR0_PTR) & USBUART_CR0_ENABLE) != 0u)
    {   /* USB block is enabled */
        USBUART_backup.enableState = 1u;

        #if(USBUART_EP_MM != USBUART__EP_MANUAL)
            USBUART_Stop_DMA(USBUART_MAX_EP);     /* Stop all DMAs */
        #endif   /*  USBUART_EP_MM != USBUART__EP_MANUAL */

        /* Ensure USB transmit enable is low (USB_USBIO_CR0.ten). - Manual Transmission - Disabled */
        USBUART_USBIO_CR0_REG &= (uint8)~USBUART_USBIO_CR0_TEN;
        CyDelayUs(0u);  /*~50ns delay */

        /* Disable the USBIO by asserting PM.USB_CR0.fsusbio_pd_n(Inverted) and pd_pullup_hv(Inverted) high. */
        USBUART_PM_USB_CR0_REG &=
                                (uint8)~(USBUART_PM_USB_CR0_PD_N | USBUART_PM_USB_CR0_PD_PULLUP_N);

        /* Disable the SIE */
        USBUART_CR0_REG &= (uint8)~USBUART_CR0_ENABLE;

        CyDelayUs(0u);  /* ~50ns delay */
        /* Store mode and Disable VRegulator*/
        USBUART_backup.mode = USBUART_CR1_REG & USBUART_CR1_REG_ENABLE;
        USBUART_CR1_REG &= (uint8)~USBUART_CR1_REG_ENABLE;

        CyDelayUs(1u);  /* 0.5 us min delay */
        /* Disable the USBIO reference by setting PM.USB_CR0.fsusbio_ref_en.*/
        USBUART_PM_USB_CR0_REG &= (uint8)~USBUART_PM_USB_CR0_REF_EN;

        /* Switch DP and DM terminals to GPIO mode and disconnect 1.5k pullup*/
        USBUART_USBIO_CR1_REG |= USBUART_USBIO_CR1_IOMODE;

        /* Disable USB in ACT PM */
        USBUART_PM_ACT_CFG_REG &= (uint8)~USBUART_PM_ACT_EN_FSUSB;
        /* Disable USB block for Standby Power Mode */
        USBUART_PM_STBY_CFG_REG &= (uint8)~USBUART_PM_STBY_EN_FSUSB;
        CyDelayUs(1u); /* min  0.5us delay required */

    }
    else
    {
        USBUART_backup.enableState = 0u;
    }

    CyExitCriticalSection(enableInterrupts);

    /* Set the DP Interrupt for wake-up from sleep mode. */
    #if(USBUART_DP_ISR_REMOVE == 0u)
        (void) CyIntSetVector(USBUART_DP_INTC_VECT_NUM, &USBUART_DP_ISR);
        CyIntSetPriority(USBUART_DP_INTC_VECT_NUM, USBUART_DP_INTC_PRIOR);
        CyIntClearPending(USBUART_DP_INTC_VECT_NUM);
        CyIntEnable(USBUART_DP_INTC_VECT_NUM);
    #endif /* (USBUART_DP_ISR_REMOVE == 0u) */
}

/*******************************************************************************
* Function Name: I2COLED_RestoreConfig
********************************************************************************
*
* Summary:
*  The Enable wakeup from Sleep Mode selection influences this function
*  implementation:
*   Unchecked: Restores the component non-retention configuration registers
*              to the state they were in before I2C_Sleep() or I2C_SaveConfig()
*              was called.
*   Checked:   Disables the backup regulator of the I2C hardware. Sets up the
*              regular component interrupt handler and generates the component
*              interrupt if it was wake up source to release the bus and
*              continue in-coming I2C transaction.
*
* Parameters:
*  None.
*
* Return:
*  None.
*
* Global Variables:
*  I2COLED_backup - The global variable used to save the component
*                            configuration and non-retention registers before
*                            exiting the sleep mode.
*
* Reentrant:
*  No.
*
* Side Effects:
*  Calling this function before I2COLED_SaveConfig() or
*  I2COLED_Sleep() will lead to unpredictable results.
*
*******************************************************************************/
void I2COLED_RestoreConfig(void) 
{
#if (I2COLED_FF_IMPLEMENTED)
    uint8 intState;

    if (I2COLED_CHECK_PWRSYS_I2C_BACKUP)
    /* Low power mode was Sleep - backup regulator is enabled */
    {
        /* Enable backup regulator in active mode */
        intState = CyEnterCriticalSection();
        I2COLED_PWRSYS_CR1_REG &= (uint8) ~I2COLED_PWRSYS_CR1_I2C_REG_BACKUP;
        CyExitCriticalSection(intState);

        /* Restore master */
        I2COLED_CFG_REG = I2COLED_backup.cfg;
    }
    else
    /* Low power mode was Hibernate - backup regulator is disabled. All registers are cleared */
    {
    #if (I2COLED_WAKEUP_ENABLED)
        /* Disable power to block before register restore */
        intState = CyEnterCriticalSection();
        I2COLED_ACT_PWRMGR_REG  &= (uint8) ~I2COLED_ACT_PWR_EN;
        I2COLED_STBY_PWRMGR_REG &= (uint8) ~I2COLED_STBY_PWR_EN;
        CyExitCriticalSection(intState);

        /* Enable component in I2C_Wakeup() after register restore */
        I2COLED_backup.enableState = I2COLED_ENABLE;
    #endif /* (I2COLED_WAKEUP_ENABLED) */

        /* Restore component registers after Hibernate */
        I2COLED_XCFG_REG    = I2COLED_backup.xcfg;
        I2COLED_CFG_REG     = I2COLED_backup.cfg;
        I2COLED_ADDR_REG    = I2COLED_backup.addr;
        I2COLED_CLKDIV1_REG = I2COLED_backup.clkDiv1;
        I2COLED_CLKDIV2_REG = I2COLED_backup.clkDiv2;
    }

#if (I2COLED_WAKEUP_ENABLED)
    I2COLED_DisableInt();
    (void) CyIntSetVector(I2COLED_ISR_NUMBER, &I2COLED_ISR);
    if (0u != I2COLED_wakeupSource)
    {
        /* Generate interrupt to process incoming transaction */
        I2COLED_SetPendingInt();
    }
    I2COLED_EnableInt();
#endif /* (I2COLED_WAKEUP_ENABLED) */

#else
    I2COLED_CFG_REG = I2COLED_backup.control;
#endif /* (I2COLED_FF_IMPLEMENTED) */

#if (I2COLED_TIMEOUT_ENABLED)
    I2COLED_TimeoutRestoreConfig();
#endif /* (I2COLED_TIMEOUT_ENABLED) */
}

/*******************************************************************************
* Function Name: SPI_Init
********************************************************************************
*
* Summary:
*  Inits/Restores default SPIM configuration provided with customizer.
*
* Parameters:
*  None.
*
* Return:
*  None.
*
* Side Effects:
*  When this function is called it initializes all of the necessary parameters
*  for execution. i.e. setting the initial interrupt mask, configuring the
*  interrupt service routine, configuring the bit-counter parameters and
*  clearing the FIFO and Status Register.
*
* Reentrant:
*  No.
*
*******************************************************************************/
void SPI_Init(void) 
{
    /* Initialize the Bit counter */
    SPI_COUNTER_PERIOD_REG = SPI_BITCTR_INIT;

    /* Init TX ISR  */
    #if(0u != SPI_INTERNAL_TX_INT_ENABLED)
        CyIntDisable         (SPI_TX_ISR_NUMBER);
        CyIntSetPriority     (SPI_TX_ISR_NUMBER,  SPI_TX_ISR_PRIORITY);
        (void) CyIntSetVector(SPI_TX_ISR_NUMBER, &SPI_TX_ISR);
    #endif /* (0u != SPI_INTERNAL_TX_INT_ENABLED) */

    /* Init RX ISR  */
    #if(0u != SPI_INTERNAL_RX_INT_ENABLED)
        CyIntDisable         (SPI_RX_ISR_NUMBER);
        CyIntSetPriority     (SPI_RX_ISR_NUMBER,  SPI_RX_ISR_PRIORITY);
        (void) CyIntSetVector(SPI_RX_ISR_NUMBER, &SPI_RX_ISR);
    #endif /* (0u != SPI_INTERNAL_RX_INT_ENABLED) */

    /* Clear any stray data from the RX and TX FIFO */
    SPI_ClearFIFO();

    #if(SPI_RX_SOFTWARE_BUF_ENABLED)
        SPI_rxBufferFull  = 0u;
        SPI_rxBufferRead  = 0u;
        SPI_rxBufferWrite = 0u;
    #endif /* (SPI_RX_SOFTWARE_BUF_ENABLED) */

    #if(SPI_TX_SOFTWARE_BUF_ENABLED)
        SPI_txBufferFull  = 0u;
        SPI_txBufferRead  = 0u;
        SPI_txBufferWrite = 0u;
    #endif /* (SPI_TX_SOFTWARE_BUF_ENABLED) */

    (void) SPI_ReadTxStatus(); /* Clear Tx status and swStatusTx */
    (void) SPI_ReadRxStatus(); /* Clear Rx status and swStatusRx */

    /* Configure TX and RX interrupt mask */
    SPI_TX_STATUS_MASK_REG = SPI_TX_INIT_INTERRUPTS_MASK;
    SPI_RX_STATUS_MASK_REG = SPI_RX_INIT_INTERRUPTS_MASK;
}

/*******************************************************************************
* Function Name: I2COLED_SaveConfig
********************************************************************************
*
* Summary:
*  The Enable wakeup from Sleep Mode selection influences this function
*  implementation:
*   Unchecked: Stores the component non-retention configuration registers.
*   Checked:   Disables the master, if it was enabled before, and enables
*              backup regulator of the I2C hardware. If a transaction intended
*              for component executes during this function call, it waits until
*              the current transaction is completed and I2C hardware is ready
*              to enter sleep mode. All subsequent I2C traffic is NAKed until
*              the device is put into sleep mode.
*
* Parameters:
*  None.
*
* Return:
*  None.
*
* Global Variables:
*  I2COLED_backup - The global variable used to save the component
*                            configuration and non-retention registers before
*                            entering the sleep mode.
*
* Reentrant:
*  No.
*
*******************************************************************************/
void I2COLED_SaveConfig(void) 
{
#if (I2COLED_FF_IMPLEMENTED)
    #if (I2COLED_WAKEUP_ENABLED)
        uint8 intState;
    #endif /* (I2COLED_WAKEUP_ENABLED) */

    /* Store registers before enter low power mode */
    I2COLED_backup.cfg     = I2COLED_CFG_REG;
    I2COLED_backup.xcfg    = I2COLED_XCFG_REG;
    I2COLED_backup.addr    = I2COLED_ADDR_REG;
    I2COLED_backup.clkDiv1 = I2COLED_CLKDIV1_REG;
    I2COLED_backup.clkDiv2 = I2COLED_CLKDIV2_REG;

#if (I2COLED_WAKEUP_ENABLED)
    /* Disable master */
    I2COLED_CFG_REG &= (uint8) ~I2COLED_ENABLE_MASTER;

    /* Enable backup regulator to keep block powered in low power mode */
    intState = CyEnterCriticalSection();
    I2COLED_PWRSYS_CR1_REG |= I2COLED_PWRSYS_CR1_I2C_REG_BACKUP;
    CyExitCriticalSection(intState);

    /* 1) Set force NACK to ignore I2C transactions;
    *  2) Wait unti I2C is ready go to Sleep; !!
    *  3) These bits are cleared on wake up.
    */
    /* Wait when block is ready for sleep */
    I2COLED_XCFG_REG |= I2COLED_XCFG_FORCE_NACK;
    while (0u == (I2COLED_XCFG_REG & I2COLED_XCFG_RDY_TO_SLEEP))
    {
    }

    /* Setup wakeup interrupt */
    I2COLED_DisableInt();
    (void) CyIntSetVector(I2COLED_ISR_NUMBER, &I2COLED_WAKEUP_ISR);
    I2COLED_wakeupSource = 0u;
    I2COLED_EnableInt();
#endif /* (I2COLED_WAKEUP_ENABLED) */

#else
    /* Store only address match bit */
    I2COLED_backup.control = (I2COLED_CFG_REG & I2COLED_CTRL_ANY_ADDRESS_MASK);
#endif /* (I2COLED_FF_IMPLEMENTED) */

#if (I2COLED_TIMEOUT_ENABLED)
    I2COLED_TimeoutSaveConfig();
#endif /* (I2COLED_TIMEOUT_ENABLED) */
}

/*******************************************************************************
* Function Name: quaddec_right_Init
********************************************************************************
*
* Summary:   
*  Inits/Restores default QuadDec configuration provided with customizer.
*
* Parameters:  
*  None.
*
* Return: 
*  None.
*
*******************************************************************************/
void quaddec_right_Init(void) 
{      
    #if (quaddec_right_COUNTER_SIZE == 32u)
      
        /* Disable Interrupt. */
        CyIntDisable(quaddec_right_ISR_NUMBER);
        
        /* Set the ISR to point to the quaddec_right_isr Interrupt. */
        CyIntSetVector(quaddec_right_ISR_NUMBER, quaddec_right_ISR);
        
        /* Set the priority. */
        CyIntSetPriority(quaddec_right_ISR_NUMBER, quaddec_right_ISR_PRIORITY);       
        
    #endif /* quaddec_right_COUNTER_SIZE == 32u */    
}