本文整理汇总了C++中CONST_INT_P函数的典型用法代码示例。如果您正苦于以下问题：C++ CONST_INT_P函数的具体用法？C++ CONST_INT_P怎么用？C++ CONST_INT_P使用的例子？那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。
在下文中一共展示了CONST_INT_P函数的15个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于系统推荐出更棒的C++代码示例。
示例1: aarch_rev16_p_1
static bool
aarch_rev16_p_1 (rtx lhs, rtx rhs, enum machine_mode mode)
{
if (GET_CODE (lhs) == AND
&& GET_CODE (XEXP (lhs, 0)) == ASHIFT
&& CONST_INT_P (XEXP (XEXP (lhs, 0), 1))
&& INTVAL (XEXP (XEXP (lhs, 0), 1)) == 8
&& REG_P (XEXP (XEXP (lhs, 0), 0))
&& CONST_INT_P (XEXP (lhs, 1))
&& GET_CODE (rhs) == AND
&& GET_CODE (XEXP (rhs, 0)) == LSHIFTRT
&& REG_P (XEXP (XEXP (rhs, 0), 0))
&& CONST_INT_P (XEXP (XEXP (rhs, 0), 1))
&& INTVAL (XEXP (XEXP (rhs, 0), 1)) == 8
&& CONST_INT_P (XEXP (rhs, 1))
&& REGNO (XEXP (XEXP (rhs, 0), 0)) == REGNO (XEXP (XEXP (lhs, 0), 0)))
{
rtx lhs_mask = XEXP (lhs, 1);
rtx rhs_mask = XEXP (rhs, 1);
return aarch_rev16_shright_mask_imm_p (rhs_mask, mode)
&& aarch_rev16_shleft_mask_imm_p (lhs_mask, mode);
}
return false;
}示例2: nds32_gen_dup_4_byte_to_word_value_aux
static rtx
nds32_gen_dup_4_byte_to_word_value_aux (rtx value, rtx value4word)
{
gcc_assert (GET_MODE (value) == QImode || CONST_INT_P (value));
if (CONST_INT_P (value))
{
unsigned HOST_WIDE_INT val = UINTVAL (value) & GET_MODE_MASK(QImode);
rtx new_val = gen_int_mode (val | (val << 8)
| (val << 16) | (val << 24), SImode);
/* Just calculate at here if it's constant value. */
emit_move_insn (value4word, new_val);
}
else
{
if (NDS32_EXT_DSP_P ())
{
/* ! prepare word
insb $tmp, $value, 1 ! $tmp <- 0x0000abab
pkbb16 $tmp6, $tmp2, $tmp2 ! $value4word <- 0xabababab */
rtx tmp = gen_reg_rtx (SImode);
convert_move (tmp, value, true);
emit_insn (
gen_insvsi_internal (tmp, gen_int_mode (0x8, SImode), tmp));
emit_insn (gen_pkbbsi_1 (value4word, tmp, tmp));
}
else
{
/* ! prepare word
andi $tmp1, $value, 0xff ! $tmp1 <- 0x000000ab
slli $tmp2, $tmp1, 8 ! $tmp2 <- 0x0000ab00
or $tmp3, $tmp1, $tmp2 ! $tmp3 <- 0x0000abab
slli $tmp4, $tmp3, 16 ! $tmp4 <- 0xabab0000
or $val4word, $tmp3, $tmp4 ! $value4word <- 0xabababab */
rtx tmp1, tmp2, tmp3, tmp4;
tmp1 = expand_binop (SImode, and_optab, value,
gen_int_mode (0xff, SImode),
NULL_RTX, 0, OPTAB_WIDEN);
tmp2 = expand_binop (SImode, ashl_optab, tmp1,
gen_int_mode (8, SImode),
NULL_RTX, 0, OPTAB_WIDEN);
tmp3 = expand_binop (SImode, ior_optab, tmp1, tmp2,
NULL_RTX, 0, OPTAB_WIDEN);
tmp4 = expand_binop (SImode, ashl_optab, tmp3,
gen_int_mode (16, SImode),
NULL_RTX, 0, OPTAB_WIDEN);
emit_insn (gen_iorsi3 (value4word, tmp3, tmp4));
}
}
return value4word;
}示例3: local_symbolic_operand_1
static inline int
local_symbolic_operand_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
#line 442 "../.././gcc/config/i386/predicates.md"
{
if (GET_CODE (op) == CONST
&& GET_CODE (XEXP (op, 0)) == PLUS
&& CONST_INT_P (XEXP (XEXP (op, 0), 1)))
op = XEXP (XEXP (op, 0), 0);
if (GET_CODE (op) == LABEL_REF)
return 1;
if (GET_CODE (op) != SYMBOL_REF)
return 0;
if (SYMBOL_REF_TLS_MODEL (op) != 0)
return 0;
if (SYMBOL_REF_LOCAL_P (op))
return 1;
/* There is, however, a not insubstantial body of code in the rest of
the compiler that assumes it can just stick the results of
ASM_GENERATE_INTERNAL_LABEL in a symbol_ref and have done. */
/* ??? This is a hack. Should update the body of the compiler to
always create a DECL an invoke targetm.encode_section_info. */
if (strncmp (XSTR (op, 0), internal_label_prefix,
internal_label_prefix_len) == 0)
return 1;
return 0;
}示例4: pic_symbolic_operand_1
static inline int
pic_symbolic_operand_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
#line 412 "../.././gcc/config/i386/predicates.md"
{
op = XEXP (op, 0);
if (TARGET_64BIT)
{
if (GET_CODE (op) == UNSPEC
&& XINT (op, 1) == UNSPEC_GOTPCREL)
return 1;
if (GET_CODE (op) == PLUS
&& GET_CODE (XEXP (op, 0)) == UNSPEC
&& XINT (XEXP (op, 0), 1) == UNSPEC_GOTPCREL)
return 1;
}
else
{
if (GET_CODE (op) == UNSPEC)
return 1;
if (GET_CODE (op) != PLUS
|| !CONST_INT_P (XEXP (op, 1)))
return 0;
op = XEXP (op, 0);
if (GET_CODE (op) == UNSPEC
&& XINT (op, 1) != UNSPEC_MACHOPIC_OFFSET)
return 1;
}
return 0;
}示例5: adjust_frame_related_expr
static void
adjust_frame_related_expr (rtx last_sp_set, rtx insn,
HOST_WIDE_INT this_adjust)
{
rtx note = find_reg_note (last_sp_set, REG_FRAME_RELATED_EXPR, NULL_RTX);
rtx new_expr = NULL_RTX;
if (note == NULL_RTX && RTX_FRAME_RELATED_P (insn))
return;
if (note
&& GET_CODE (XEXP (note, 0)) == SEQUENCE
&& XVECLEN (XEXP (note, 0), 0) >= 2)
{
rtx expr = XEXP (note, 0);
rtx last = XVECEXP (expr, 0, XVECLEN (expr, 0) - 1);
int i;
if (GET_CODE (last) == SET
&& RTX_FRAME_RELATED_P (last) == RTX_FRAME_RELATED_P (insn)
&& SET_DEST (last) == stack_pointer_rtx
&& GET_CODE (SET_SRC (last)) == PLUS
&& XEXP (SET_SRC (last), 0) == stack_pointer_rtx
&& CONST_INT_P (XEXP (SET_SRC (last), 1)))
{
XEXP (SET_SRC (last), 1)
= GEN_INT (INTVAL (XEXP (SET_SRC (last), 1)) + this_adjust);
return;
}
new_expr = gen_rtx_SEQUENCE (VOIDmode,
rtvec_alloc (XVECLEN (expr, 0) + 1));
for (i = 0; i < XVECLEN (expr, 0); i++)
XVECEXP (new_expr, 0, i) = XVECEXP (expr, 0, i);
}
else
{
new_expr = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (2));
if (note)
XVECEXP (new_expr, 0, 0) = XEXP (note, 0);
else
{
rtx expr = copy_rtx (single_set_for_csa (last_sp_set));
XEXP (SET_SRC (expr), 1)
= GEN_INT (INTVAL (XEXP (SET_SRC (expr), 1)) - this_adjust);
RTX_FRAME_RELATED_P (expr) = 1;
XVECEXP (new_expr, 0, 0) = expr;
}
}
XVECEXP (new_expr, 0, XVECLEN (new_expr, 0) - 1)
= copy_rtx (single_set_for_csa (insn));
RTX_FRAME_RELATED_P (XVECEXP (new_expr, 0, XVECLEN (new_expr, 0) - 1))
= RTX_FRAME_RELATED_P (insn);
if (note)
XEXP (note, 0) = new_expr;
else
add_reg_note (last_sp_set, REG_FRAME_RELATED_EXPR, new_expr);
}示例6: aarch_rev16_shleft_mask_imm_p
bool
aarch_rev16_shleft_mask_imm_p (rtx val, enum machine_mode mode)
{
return CONST_INT_P (val)
&& INTVAL (val)
== trunc_int_for_mode (HOST_WIDE_INT_C (0xff00ff00ff00ff00),
mode);
}示例7: nds32_expand_strlen
bool
nds32_expand_strlen (rtx result, rtx str,
rtx target_char, rtx align ATTRIBUTE_UNUSED)
{
rtx base_reg, backup_base_reg;
rtx ffb_result;
rtx target_char_ptr, length;
rtx loop_label, tmp;
if (optimize_size || optimize < 3)
return false;
gcc_assert (MEM_P (str));
gcc_assert (CONST_INT_P (target_char) || REG_P (target_char));
base_reg = copy_to_mode_reg (SImode, XEXP (str, 0));
loop_label = gen_label_rtx ();
ffb_result = gen_reg_rtx (Pmode);
tmp = gen_reg_rtx (SImode);
backup_base_reg = gen_reg_rtx (SImode);
/* Emit loop version of strlen.
move $backup_base, $base
.Lloop:
lmw.bim $tmp, [$base], $tmp, 0
ffb $ffb_result, $tmp, $target_char ! is there $target_char?
beqz $ffb_result, .Lloop
add $last_char_ptr, $base, $ffb_result
sub $length, $last_char_ptr, $backup_base */
/* move $backup_base, $base */
emit_move_insn (backup_base_reg, base_reg);
/* .Lloop: */
emit_label (loop_label);
/* lmw.bim $tmp, [$base], $tmp, 0 */
emit_insn (gen_unaligned_load_update_base_w (base_reg, tmp, base_reg));
/* ffb $ffb_result, $tmp, $target_char ! is there $target_char? */
emit_insn (gen_unspec_ffb (ffb_result, tmp, target_char));
/* beqz $ffb_result, .Lloop */
emit_cmp_and_jump_insns (ffb_result, const0_rtx, EQ, NULL,
SImode, 1, loop_label);
/* add $target_char_ptr, $base, $ffb_result */
target_char_ptr = expand_binop (Pmode, add_optab, base_reg,
ffb_result, NULL_RTX, 0, OPTAB_WIDEN);
/* sub $length, $target_char_ptr, $backup_base */
length = expand_binop (Pmode, sub_optab, target_char_ptr,
backup_base_reg, NULL_RTX, 0, OPTAB_WIDEN);
emit_move_insn (result, length);
return true;
}示例8: aligned_operand_1
static inline int
aligned_operand_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
#line 825 "../.././gcc/config/i386/predicates.md"
{
struct ix86_address parts;
int ok;
/* Registers and immediate operands are always "aligned". */
if (GET_CODE (op) != MEM)
return 1;
/* All patterns using aligned_operand on memory operands ends up
in promoting memory operand to 64bit and thus causing memory mismatch. */
if (TARGET_MEMORY_MISMATCH_STALL && !optimize_size)
return 0;
/* Don't even try to do any aligned optimizations with volatiles. */
if (MEM_VOLATILE_P (op))
return 0;
if (MEM_ALIGN (op) >= 32)
return 1;
op = XEXP (op, 0);
/* Pushes and pops are only valid on the stack pointer. */
if (GET_CODE (op) == PRE_DEC
|| GET_CODE (op) == POST_INC)
return 1;
/* Decode the address. */
ok = ix86_decompose_address (op, &parts);
gcc_assert (ok);
/* Look for some component that isn't known to be aligned. */
if (parts.index)
{
if (REGNO_POINTER_ALIGN (REGNO (parts.index)) * parts.scale < 32)
return 0;
}
if (parts.base)
{
if (REGNO_POINTER_ALIGN (REGNO (parts.base)) < 32)
return 0;
}
if (parts.disp)
{
if (!CONST_INT_P (parts.disp)
|| (INTVAL (parts.disp) & 3) != 0)
return 0;
}
/* Didn't find one -- this must be an aligned address. */
return 1;
}示例9: aarch64_simd_expand_builtin
/* Expand an AArch64 AdvSIMD builtin(intrinsic). */
rtx
aarch64_simd_expand_builtin (int fcode, tree exp, rtx target)
{
aarch64_simd_builtin_datum *d =
&aarch64_simd_builtin_data[fcode - (AARCH64_SIMD_BUILTIN_BASE + 1)];
enum insn_code icode = d->code;
builtin_simd_arg args[SIMD_MAX_BUILTIN_ARGS];
int num_args = insn_data[d->code].n_operands;
int is_void = 0;
int k;
is_void = !!(d->qualifiers[0] & qualifier_void);
num_args += is_void;
for (k = 1; k < num_args; k++)
{
/* We have four arrays of data, each indexed in a different fashion.
qualifiers - element 0 always describes the function return type.
operands - element 0 is either the operand for return value (if
the function has a non-void return type) or the operand for the
first argument.
expr_args - element 0 always holds the first argument.
args - element 0 is always used for the return type. */
int qualifiers_k = k;
int operands_k = k - is_void;
int expr_args_k = k - 1;
if (d->qualifiers[qualifiers_k] & qualifier_lane_index)
args[k] = SIMD_ARG_LANE_INDEX;
else if (d->qualifiers[qualifiers_k] & qualifier_immediate)
args[k] = SIMD_ARG_CONSTANT;
else if (d->qualifiers[qualifiers_k] & qualifier_maybe_immediate)
{
rtx arg
= expand_normal (CALL_EXPR_ARG (exp,
(expr_args_k)));
/* Handle constants only if the predicate allows it. */
bool op_const_int_p =
(CONST_INT_P (arg)
&& (*insn_data[icode].operand[operands_k].predicate)
(arg, insn_data[icode].operand[operands_k].mode));
args[k] = op_const_int_p ? SIMD_ARG_CONSTANT : SIMD_ARG_COPY_TO_REG;
}
else
args[k] = SIMD_ARG_COPY_TO_REG;
}
args[k] = SIMD_ARG_STOP;
/* The interface to aarch64_simd_expand_args expects a 0 if
the function is void, and a 1 if it is not. */
return aarch64_simd_expand_args
(target, icode, !is_void, exp, &args[1]);
}示例10: shared_const_p
bool
shared_const_p (const_rtx orig)
{
gcc_assert (GET_CODE (orig) == CONST);
/* CONST can be shared if it contains a SYMBOL_REF. If it contains
a LABEL_REF, it isn't sharable. */
return (GET_CODE (XEXP (orig, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (orig, 0), 0)) == SYMBOL_REF
&& CONST_INT_P(XEXP (XEXP (orig, 0), 1)));
}示例11: nds32_expand_movmemsi_loop
static bool
nds32_expand_movmemsi_loop (rtx dstmem, rtx srcmem,
rtx size, rtx alignment)
{
if (CONST_INT_P (size))
return nds32_expand_movmemsi_loop_known_size (dstmem, srcmem,
size, alignment);
else
return nds32_expand_movmemsi_loop_unknown_size (dstmem, srcmem,
size, alignment);
}示例12: form_sum
/* Compute the sum of X and Y, making canonicalizations assumed in an
address, namely: sum constant integers, surround the sum of two
constants with a CONST, put the constant as the second operand, and
group the constant on the outermost sum.
This routine assumes both inputs are already in canonical form. */
static rtx
form_sum (rtx x, rtx y)
{
machine_mode mode = GET_MODE (x);
if (mode == VOIDmode)
mode = GET_MODE (y);
if (mode == VOIDmode)
mode = Pmode;
if (CONST_INT_P (x))
return plus_constant (mode, y, INTVAL (x));
else if (CONST_INT_P (y))
return plus_constant (mode, x, INTVAL (y));
else if (CONSTANT_P (x))
std::swap (x, y);
if (GET_CODE (x) == PLUS && CONSTANT_P (XEXP (x, 1)))
return form_sum (XEXP (x, 0), form_sum (XEXP (x, 1), y));
/* Note that if the operands of Y are specified in the opposite
order in the recursive calls below, infinite recursion will
occur. */
if (GET_CODE (y) == PLUS && CONSTANT_P (XEXP (y, 1)))
return form_sum (form_sum (x, XEXP (y, 0)), XEXP (y, 1));
/* If both constant, encapsulate sum. Otherwise, just form sum. A
constant will have been placed second. */
if (CONSTANT_P (x) && CONSTANT_P (y))
{
if (GET_CODE (x) == CONST)
x = XEXP (x, 0);
if (GET_CODE (y) == CONST)
y = XEXP (y, 0);
return gen_rtx_CONST (VOIDmode, gen_rtx_PLUS (mode, x, y));
}
return gen_rtx_PLUS (mode, x, y);
}示例13: sdbout_reg_parms
static void
sdbout_reg_parms (tree parms)
{
for (; parms; parms = TREE_CHAIN (parms))
if (DECL_NAME (parms))
{
const char *name = IDENTIFIER_POINTER (DECL_NAME (parms));
/* Report parms that live in registers during the function
but were passed in memory. */
if (REG_P (DECL_RTL (parms))
&& REGNO (DECL_RTL (parms)) < FIRST_PSEUDO_REGISTER
&& PARM_PASSED_IN_MEMORY (parms))
{
if (name == 0 || *name == 0)
name = gen_fake_label ();
PUT_SDB_DEF (name);
PUT_SDB_INT_VAL (DBX_REGISTER_NUMBER (REGNO (DECL_RTL (parms))));
PUT_SDB_SCL (C_REG);
PUT_SDB_TYPE (plain_type (TREE_TYPE (parms)));
PUT_SDB_ENDEF;
}
/* Report parms that live in memory but not where they were passed. */
else if (MEM_P (DECL_RTL (parms))
&& GET_CODE (XEXP (DECL_RTL (parms), 0)) == PLUS
&& CONST_INT_P (XEXP (XEXP (DECL_RTL (parms), 0), 1))
&& PARM_PASSED_IN_MEMORY (parms)
&& ! rtx_equal_p (DECL_RTL (parms), DECL_INCOMING_RTL (parms)))
{
#if 0 /* ??? It is not clear yet what should replace this. */
int offset = DECL_OFFSET (parms) / BITS_PER_UNIT;
/* A parm declared char is really passed as an int,
so it occupies the least significant bytes.
On a big-endian machine those are not the low-numbered ones. */
if (BYTES_BIG_ENDIAN
&& offset != -1
&& TREE_TYPE (parms) != DECL_ARG_TYPE (parms))
offset += (GET_MODE_SIZE (TYPE_MODE (DECL_ARG_TYPE (parms)))
- GET_MODE_SIZE (GET_MODE (DECL_RTL (parms))));
if (INTVAL (XEXP (XEXP (DECL_RTL (parms), 0), 1)) != offset) {...}
#endif
{
if (name == 0 || *name == 0)
name = gen_fake_label ();
PUT_SDB_DEF (name);
PUT_SDB_INT_VAL (DEBUGGER_AUTO_OFFSET
(XEXP (DECL_RTL (parms), 0)));
PUT_SDB_SCL (C_AUTO);
PUT_SDB_TYPE (plain_type (TREE_TYPE (parms)));
PUT_SDB_ENDEF;
}
}
}示例14: arm_rtx_shift_left_p
/* Return TRUE if X is either an arithmetic shift left, or
is a multiplication by a power of two. */
bool
arm_rtx_shift_left_p (rtx x)
{
enum rtx_code code = GET_CODE (x);
if (code == MULT && CONST_INT_P (XEXP (x, 1))
&& exact_log2 (INTVAL (XEXP (x, 1))) > 0)
return true;
if (code == ASHIFT)
return true;
return false;
}示例15: dw2_assemble_integer
void
dw2_assemble_integer (int size, rtx x)
{
const char *op = integer_asm_op (size, FALSE);
if (op)
{
fputs (op, asm_out_file);
if (CONST_INT_P (x))
fprint_whex (asm_out_file, (unsigned HOST_WIDE_INT) INTVAL (x));
else
output_addr_const (asm_out_file, x);
}
else
assemble_integer (x, size, BITS_PER_UNIT, 1);
}