C++ CLOCK_EnableClock函数代码示例

/*!
 * @brief Initialize all pins used in this example
 *
 * @param disablePortClockAfterInit disable port clock after pin
 * initialization or not.
 */
void BOARD_InitPins(void)
{
	/* Initialize UART1 pins below */
	/* Ungate the port clock */
	/* Enable the clock to the PORT module that the LED is on. */
	CLOCK_EnableClock(kCLOCK_PortE);
	CLOCK_EnableClock(kCLOCK_PortB);

	/* SET USB pins */
	/* Affects PORTB_PCR16 register */
	PORT_SetPinMux(PORTB, 16u, kPORT_MuxAlt3);
	/* Affects PORTB_PCR17 register */
	PORT_SetPinMux(PORTB, 17u, kPORT_MuxAlt3);


    /* Led pin mux Configuration */
    PORT_SetPinMux(PORTB, 22U, kPORT_MuxAsGpio);
    PORT_SetPinMux(PORTE, 26U, kPORT_MuxAsGpio);
    PORT_SetPinMux(PORTB, 21U, kPORT_MuxAsGpio);

    //debug
    PORT_SetPinMux(PORTE, 24U, kPORT_MuxAsGpio);


    /* Initialize LED pins below */
    LED_RED_INIT(1U);
    LED_GREEN_INIT(1U);
    LED_BLUE_INIT(1U);

}

void BOARD_InitPins(void)
{
    /* Declare and initialise for pull up configuration */
    port_pin_config_t pinConfig = {0};
    pinConfig.pullSelect = kPORT_PullUp;
#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN
    pinConfig.openDrainEnable = kPORT_OpenDrainEnable;
#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */

    /* Initialize LPUART0 pins below */
    /* Ungate the port clock */
    CLOCK_EnableClock(kCLOCK_PortA);
    /* Affects PORTA_PCR1 register */
    PORT_SetPinMux(PORTA, 1u, kPORT_MuxAlt2);
    /* Affects PORTA_PCR2 register */
    PORT_SetPinMux(PORTA, 2u, kPORT_MuxAlt2);

    /* Ungate the port clock */
    CLOCK_EnableClock(kCLOCK_PortB);
    /* I2C0 pull up resistor setting */
    PORT_SetPinConfig(PORTB, 2U, &pinConfig);
    PORT_SetPinConfig(PORTB, 3U, &pinConfig);
    /* I2C0 PIN_MUX Configuration */
    PORT_SetPinMux(PORTB, 2U, kPORT_MuxAlt2);
    PORT_SetPinMux(PORTB, 3U, kPORT_MuxAlt2);

    /* Ungate the port clock */
    CLOCK_EnableClock(kCLOCK_PortE);
    /* I2C1 pull up resistor setting */
    PORT_SetPinConfig(PORTE, 0U, &pinConfig);
    PORT_SetPinConfig(PORTE, 1U, &pinConfig);
    /* I2C1 PIN_MUX Configuration */
    PORT_SetPinMux(PORTE, 0U, kPORT_MuxAlt6);
    PORT_SetPinMux(PORTE, 1U, kPORT_MuxAlt6);
}

/*******************************************************************************
 * Code
 ******************************************************************************/
void BOARD_InitPins(void)
{
    /* Declare and initialise for pull up configuration */
    port_pin_config_t pinConfig = {0};
    pinConfig.pullSelect = kPORT_PullUp;
    pinConfig.openDrainEnable = kPORT_OpenDrainEnable;

    /* Initialize UART1 pins below */
    /* Ungate the port clock */
    CLOCK_EnableClock(kCLOCK_PortE);
    /* Affects PORTE_PCR0 register */
    PORT_SetPinMux(PORTE, 0U, kPORT_MuxAlt3);
    /* Affects PORTE_PCR1 register */
    PORT_SetPinMux(PORTE, 1U, kPORT_MuxAlt3);

    /* Ungate the port clock */
    CLOCK_EnableClock(kCLOCK_PortB);
    /* I2C0 pull up resistor setting */
    PORT_SetPinConfig(PORTB, 2U, &pinConfig);
    PORT_SetPinConfig(PORTB, 3U, &pinConfig);
    /* I2C0 PIN_MUX Configuration */
    PORT_SetPinMux(PORTB, 2U, kPORT_MuxAlt2);
    PORT_SetPinMux(PORTB, 3U, kPORT_MuxAlt2);

    /* Ungate the port clock */
    CLOCK_EnableClock(kCLOCK_PortC);
    /* I2C1 pull up resistor setting */
    PORT_SetPinConfig(PORTC, 10U, &pinConfig);
    PORT_SetPinConfig(PORTC, 11U, &pinConfig);
    /* I2C1 PIN_MUX Configuration */
    PORT_SetPinMux(PORTC, 10U, kPORT_MuxAlt2);
    PORT_SetPinMux(PORTC, 11U, kPORT_MuxAlt2);
}

void BOARD_InitPins(void)
{
    port_pin_config_t config = {0};

    /* Initialize UART1 pins below */
    /* Ungate the port clock */
    CLOCK_EnableClock(kCLOCK_PortE);

    /* Affects PORTE_PCR0 register */
    PORT_SetPinMux(PORTE, 0U, kPORT_MuxAlt3);
    /* Affects PORTE_PCR1 register */
    PORT_SetPinMux(PORTE, 1U, kPORT_MuxAlt3);

    CLOCK_EnableClock(kCLOCK_PortB);
    CLOCK_EnableClock(kCLOCK_PortC);

    /* Sets PORTC_PCR3 as SPI_PCS */
    config.mux = kPORT_MuxAlt2;
    PORT_SetPinConfig(PORTB, 10U, &config);

    /* Sets PORTC_PCR5 as SPI_SCK. */
    PORT_SetPinConfig(PORTB, 11U, &config);

    /* Sets PORTD_PCR3 as SPI_MISO */
    PORT_SetPinConfig(PORTB, 16U, &config);

    /* Sets PORTD_PCR2 as SPI_MOSI */
    PORT_SetPinConfig(PORTB, 17U, &config);

    /* Sets card detection pin as GPIO */
    config.pullSelect = kPORT_PullUp;
    config.mux = kPORT_MuxAsGpio;
    PORT_SetPinConfig(PORTE, 6U, &config);
}

SECTION("itcm") int rt_hw_flexspi_init(void)
{
    flexspi_config_t config;
    status_t status;
    rt_uint32_t level;
    level = rt_hw_interrupt_disable();
    // Set flexspi root clock to 166MHZ.
    const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U};

    CLOCK_InitUsb1Pll(&g_ccmConfigUsbPll);
    CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 26);   /* Set PLL3 PFD0 clock 332MHZ. */
    CLOCK_SetMux(kCLOCK_FlexspiMux, 0x3); /* Choose PLL3 PFD0 clock as flexspi source clock. */
    
    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3);   /* flexspi clock 83M, DDR mode, internal clock 42M. */

    
    /*Get FLEXSPI default settings and configure the flexspi. */
    FLEXSPI_GetDefaultConfig(&config);

    /*Set AHB buffer size for reading data through AHB bus. */
    config.ahbConfig.enableAHBPrefetch = true;
    /*Allow AHB read start address do not follow the alignment requirement. */
    config.ahbConfig.enableReadAddressOpt = true;
    /* enable diff clock and DQS */
    config.enableSckBDiffOpt = true;
    config.rxSampleClock = kFLEXSPI_ReadSampleClkExternalInputFromDqsPad;
    config.enableCombination = true;
    FLEXSPI_Init(FLEXSPI, &config);
    
    /* Configure flash settings according to serial flash feature. */
    FLEXSPI_SetFlashConfig(FLEXSPI, &deviceconfig, kFLEXSPI_PortA1);
    
    /* Update LUT table. */
    FLEXSPI_UpdateLUT(FLEXSPI, 0, customLUT, CUSTOM_LUT_LENGTH);

    /* Do software reset. */
    FLEXSPI_SoftwareReset(FLEXSPI);

    status = flexspi_nor_hyperflash_cfi(FLEXSPI);
    /* Get vendor ID. */
    if (status != kStatus_Success)
    {
        FLEXSPI_Enable(FLEXSPI, false);
        CLOCK_DisableClock(FLEXSPI_CLOCK);
        CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* flexspi clock 332M, DDR mode, internal clock 166M. */
        CLOCK_EnableClock(FLEXSPI_CLOCK);
        FLEXSPI_Enable(FLEXSPI, true);
        FLEXSPI_SoftwareReset(FLEXSPI);
        rt_hw_interrupt_enable(level);
        return status;
    }
    FLEXSPI_Enable(FLEXSPI, false);
    CLOCK_DisableClock(FLEXSPI_CLOCK);
    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* flexspi clock 332M, DDR mode, internal clock 166M. */
    CLOCK_EnableClock(FLEXSPI_CLOCK);
    FLEXSPI_Enable(FLEXSPI, true);
    FLEXSPI_SoftwareReset(FLEXSPI);
    rt_hw_interrupt_enable(level);
    return 0;
}

/*!
 * brief Ungates the LPTMR clock and configures the peripheral for a basic operation.
 *
 * note This API should be called at the beginning of the application using the LPTMR driver.
 *
 * param base   LPTMR peripheral base address
 * param config A pointer to the LPTMR configuration structure.
 */
void LPTMR_Init(LPTMR_Type *base, const lptmr_config_t *config)
{
    assert(config);

#if defined(LPTMR_CLOCKS)
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)

    uint32_t instance = LPTMR_GetInstance(base);

    /* Ungate the LPTMR clock*/
    CLOCK_EnableClock(s_lptmrClocks[instance]);
#if defined(LPTMR_PERIPH_CLOCKS)
    CLOCK_EnableClock(s_lptmrPeriphClocks[instance]);
#endif

#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
#endif /* LPTMR_CLOCKS */

    /* Configure the timers operation mode and input pin setup */
    base->CSR = (LPTMR_CSR_TMS(config->timerMode) | LPTMR_CSR_TFC(config->enableFreeRunning) |
                 LPTMR_CSR_TPP(config->pinPolarity) | LPTMR_CSR_TPS(config->pinSelect));

    /* Configure the prescale value and clock source */
    base->PSR = (LPTMR_PSR_PRESCALE(config->value) | LPTMR_PSR_PBYP(config->bypassPrescaler) |
                 LPTMR_PSR_PCS(config->prescalerClockSource));
}

void PlatformInit(int argc, char *argv[])
{
    uint32_t temp, tempTrim;
    uint8_t  revId;

    /* enable clock for PORTs */
    CLOCK_EnableClock(kCLOCK_PortA);
    CLOCK_EnableClock(kCLOCK_PortB);
    CLOCK_EnableClock(kCLOCK_PortC);

    SIM->SCGC6 |= (SIM_SCGC6_DMAMUX_MASK); /* Enable clock to DMA_MUX (SIM module) */
    SIM->SCGC7 |= (SIM_SCGC7_DMA_MASK);

    /* Obtain REV ID from SIM */
    revId = (uint8_t)((SIM->SDID & SIM_SDID_REVID_MASK) >> SIM_SDID_REVID_SHIFT);

    if (revId == 0)
    {
        tempTrim = RSIM->ANA_TRIM;
        RSIM->ANA_TRIM |= RSIM_ANA_TRIM_BB_LDO_XO_TRIM_MASK; /* max trim for BB LDO for XO */
    }

    /* Turn on clocks for the XCVR */
    /* Enable RF OSC in RSIM and wait for ready */
    temp = RSIM->CONTROL;
    temp &= ~RSIM_CONTROL_RF_OSC_EN_MASK;
    RSIM->CONTROL = temp | RSIM_CONTROL_RF_OSC_EN(1);
    /* Prevent XTAL_OUT_EN from generating XTAL_OUT request */
    RSIM->RF_OSC_CTRL |= RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_MASK;

    /* wait for RF_OSC_READY */
    while ((RSIM->CONTROL & RSIM_CONTROL_RF_OSC_READY_MASK) == 0)
    {
    }

    if (revId == 0)
    {
        SIM->SCGC5 |= SIM_SCGC5_PHYDIG_MASK;
        XCVR_TSM->OVRD0 |= XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_EN_MASK |
                           XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_MASK; /* Force ADC DAC LDO on to prevent BGAP failure */
        /* Reset LDO trim settings */
        RSIM->ANA_TRIM = tempTrim;
    } /* Workaround for Rev 1.0 XTAL startup and ADC analog diagnostics circuitry */

    /* Init board clock */
    BOARD_BootClockRUN();

    kw41zAlarmInit();
    kw41zRandomInit();
    kw41zRadioInit();

    otPlatUartEnable();

    (void)argc;
    (void)argv;
}

void INPUTMUX_Init(INPUTMUX_Type *base)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
#if defined(FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE) && FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE
    CLOCK_EnableClock(kCLOCK_Sct);
    CLOCK_EnableClock(kCLOCK_Dma);
#else
    CLOCK_EnableClock(kCLOCK_InputMux);
#endif /* FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE */
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}

void RNGA_Init(RNG_Type *base)
{
    /* Enable the clock gate. */
    CLOCK_EnableClock(kCLOCK_Rnga0);
    CLOCK_DisableClock(kCLOCK_Rnga0); /* To solve the release version on twrkm43z75m */
    CLOCK_EnableClock(kCLOCK_Rnga0);

    /* Reset the registers for RNGA module to reset state. */
    RNG_WR_CR(base, 0);
    /* Enables the RNGA random data generation and loading.*/
    RNG_WR_CR_GO(base, 1);
}

void BOARD_InitPins(void)
{
    /* Set EXTAL0/XTAL0 pinmux. */
    CLOCK_EnableClock(kCLOCK_PortA);
    PORT_SetPinMux(PORTA, 18U, kPORT_PinDisabledOrAnalog);
    PORT_SetPinMux(PORTA, 19U, kPORT_PinDisabledOrAnalog);

    /* Enable LED port clock */
    CLOCK_EnableClock(kCLOCK_PortA);
    /* Led pin mux Configuration */
    PORT_SetPinMux(PORTA, 13U, kPORT_MuxAsGpio);
}

/*!
 * @brief Initialize all pins used in this example
 */
void BOARD_InitPins(void)
{
    /* Ungate the port clock */
    CLOCK_EnableClock(kCLOCK_PortE);

    /* Affects PORTE_PCR0 register */
    PORT_SetPinMux(PORTE, 0U, kPORT_MuxAlt3);
    /* Affects PORTE_PCR1 register */
    PORT_SetPinMux(PORTE, 1U, kPORT_MuxAlt3);

    CLOCK_EnableClock(kCLOCK_PortB);
    PORT_SetPinMux(PORTB, 0U, kPORT_PinDisabledOrAnalog);
}

void modem_init() {
  const gpio_pin_config_t OUTTRUE = {kGPIO_DigitalOutput, true};
  const gpio_pin_config_t IN = {kGPIO_DigitalInput, false};

  // initialize BOARD_CELL pins
  CLOCK_EnableClock(BOARD_CELL_UART_PORT_CLOCK);
  PORT_SetPinMux(BOARD_CELL_UART_PORT, BOARD_CELL_UART_TX_PIN, BOARD_CELL_UART_TX_ALT);
  PORT_SetPinMux(BOARD_CELL_UART_PORT, BOARD_CELL_UART_RX_PIN, BOARD_CELL_UART_RX_ALT);

  CLOCK_EnableClock(BOARD_CELL_PIN_PORT_CLOCK);
  PORT_SetPinMux(BOARD_CELL_PIN_PORT, BOARD_CELL_STATUS_PIN, kPORT_MuxAsGpio);
  GPIO_PinInit(BOARD_CELL_PIN_GPIO, BOARD_CELL_STATUS_PIN, &IN);

#if BOARD_CELL_RESET_PIN
  PORT_SetPinMux(BOARD_CELL_PIN_PORT, BOARD_CELL_RESET_PIN, kPORT_MuxAsGpio);
  GPIO_PinInit(BOARD_CELL_PIN_GPIO, BOARD_CELL_RESET_PIN, &OUTTRUE);
#endif

  PORT_SetPinMux(BOARD_CELL_PIN_PORT, BOARD_CELL_PWRKEY_PIN, kPORT_MuxAsGpio);
  GPIO_PinInit(BOARD_CELL_PIN_GPIO, BOARD_CELL_PWRKEY_PIN, &OUTTRUE);

  // the ring identifier is optional, only use if a pin and port exists
#if BOARD_CELL_RI_PIN
  PORT_SetPinMux(BOARD_CELL_PIN_PORT, BOARD_CELL_RI_PIN, kPORT_MuxAsGpio);
  GPIO_PinInit(BOARD_CELL_PIN_GPIO, BOARD_CELL_RI_PIN, &IN);
#endif

#if BOARD_CELL_PWR_DOMAIN
  const gpio_pin_config_t OUTFALSE = {kGPIO_DigitalOutput, false};

  CLOCK_EnableClock(BOARD_CELL_PWR_EN_CLOCK);
  PORT_SetPinMux(BOARD_CELL_PWR_EN_PORT, BOARD_CELL_PWR_EN_PIN, kPORT_MuxAsGpio);
  GPIO_PinInit(BOARD_CELL_PWR_EN_GPIO, BOARD_CELL_PWR_EN_PIN, &OUTFALSE);
#endif


  // configure uart driver connected to the SIM800H
  lpuart_config_t lpuart_config;
  LPUART_GetDefaultConfig(&lpuart_config);
  lpuart_config.baudRate_Bps = 115200;
  lpuart_config.parityMode = kLPUART_ParityDisabled;
  lpuart_config.stopBitCount = kLPUART_OneStopBit;
  LPUART_Init(BOARD_CELL_UART, &lpuart_config, BOARD_CELL_PORT_CLOCK_FREQ);
  LPUART_EnableRx(BOARD_CELL_UART, true);
  LPUART_EnableTx(BOARD_CELL_UART, true);

  LPUART_EnableInterrupts(BOARD_CELL_UART, kLPUART_RxDataRegFullInterruptEnable);
  EnableIRQ(BOARD_CELL_UART_IRQ);
}

void BOARD_InitPins(void)
{
    /* Initialize LPUART0 pins below */
    /* Ungate the port clock */
    CLOCK_EnableClock(kCLOCK_PortA);
    /* Affects PORTA_PCR1 register */
    PORT_SetPinMux(PORTA, 1U, kPORT_MuxAlt2);
    /* Affects PORTA_PCR2 register */
    PORT_SetPinMux(PORTA, 2U, kPORT_MuxAlt2);

    /* Ungate the port clock */
    CLOCK_EnableClock(kCLOCK_PortE);
    /* PTE31 TPM0 channel 4 -- GREEN LED */
    PORT_SetPinMux(PORTE, 31U, kPORT_MuxAlt3);
}

/*******************************************************************************
 * Code
 ******************************************************************************/
void initialize_enet_hardware(void)
{
    port_pin_config_t configENET = {0};

    /* Disable MPU. */
    MPU->CESR &= ~MPU_CESR_VLD_MASK;

    CLOCK_EnableClock(kCLOCK_PortC);
    CLOCK_EnableClock(kCLOCK_PortB);
    /* Affects PORTC_PCR16 register */
    PORT_SetPinMux(PORTC, 16u, kPORT_MuxAlt4);
    /* Affects PORTC_PCR17 register */
    PORT_SetPinMux(PORTC, 17u, kPORT_MuxAlt4);
    /* Affects PORTC_PCR18 register */
    PORT_SetPinMux(PORTC, 18u, kPORT_MuxAlt4);
    /* Affects PORTC_PCR19 register */
    PORT_SetPinMux(PORTC, 19u, kPORT_MuxAlt4);
    /* Affects PORTB_PCR1 register */
    PORT_SetPinMux(PORTB, 1u, kPORT_MuxAlt4);

    configENET.openDrainEnable = kPORT_OpenDrainEnable;
    configENET.mux = kPORT_MuxAlt4;
    configENET.pullSelect = kPORT_PullUp;
    /* Ungate the port clock */
    CLOCK_EnableClock(kCLOCK_PortA);
    /* Affects PORTB_PCR0 register */
    PORT_SetPinConfig(PORTB, 0u, &configENET);

    /* Affects PORTA_PCR13 register */
    PORT_SetPinMux(PORTA, 13u, kPORT_MuxAlt4);
    /* Affects PORTA_PCR12 register */
    PORT_SetPinMux(PORTA, 12u, kPORT_MuxAlt4);
    /* Affects PORTA_PCR14 register */
    PORT_SetPinMux(PORTA, 14u, kPORT_MuxAlt4);
    /* Affects PORTA_PCR5 register */
    PORT_SetPinMux(PORTA, 5u, kPORT_MuxAlt4);
    /* Affects PORTA_PCR16 register */
    PORT_SetPinMux(PORTA, 16u, kPORT_MuxAlt4);
    /* Affects PORTA_PCR17 register */
    PORT_SetPinMux(PORTA, 17u, kPORT_MuxAlt4);
    /* Affects PORTA_PCR15 register */
    PORT_SetPinMux(PORTA, 15u, kPORT_MuxAlt4);
    /* Affects PORTA_PCR28 register */
    PORT_SetPinMux(PORTA, 28u, kPORT_MuxAlt4);

    /* Select the Ethernet timestamp clock source */
    CLOCK_SetEnetTime0Clock(0x2);
}

void KPP_Init(KPP_Type *base, kpp_config_t *configure)
{
    assert(configure);

    uint32_t instance = KPP_GetInstance(base);

#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
    /* Un-gate sdram controller clock. */
    CLOCK_EnableClock(s_kppClock[KPP_GetInstance(base)]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */

    /* Clear all. */
    base->KPSR &= ~(KPP_KPSR_KRIE_MASK | KPP_KPSR_KDIE_MASK);

    /* Enable the keypad row and set the column strobe output to open drain. */
    base->KPCR = KPP_KPCR_KRE(configure->activeRow);
    base->KPDR = KPP_KPDR_KCD((uint8_t)~(configure->activeColumn));
    base->KPCR |= KPP_KPCR_KCO(configure->activeColumn);

    /* Set the input direction for row and output direction for column. */
    base->KDDR = KPP_KDDR_KCDD(configure->activeColumn) | KPP_KDDR_KRDD((uint8_t)~(configure->activeRow));

    /* Clear the status flag and enable the interrupt. */
    base->KPSR =
        KPP_KPSR_KPKR_MASK | KPP_KPSR_KPKD_MASK | KPP_KPSR_KDSC_MASK | configure->interrupt;

    if (configure->interrupt)
    {
        /* Enable at the Interrupt */
        EnableIRQ(s_kppIrqs[instance]);
    }
}