C++ CHECK_RETVAL函数代码示例

/**
 * Write registers. addr is an array of addresses, and those addresses can be
 * in any order, though it is recommended that they are in sequential order
 * where possible, as this reduces number of JTAG commands to transfer.
 *
 * @param jtag_info
 * @param type		Type of registers to write: core or aux.
 * @param addr		Array of registers numbers.
 * @param count		Amount of registers in arrays.
 * @param values	Array of register values.
 */
static int arc_jtag_write_registers(struct arc_jtag *jtag_info, reg_type_t type,
	uint32_t *addr, uint32_t count, const uint32_t *buffer)
{
	unsigned int i;

	LOG_DEBUG("Writing to %s registers: addr[0]=0x%" PRIx32 ";count=%" PRIu32
			  ";buffer[0]=0x%08" PRIx32,
		(type == ARC_JTAG_CORE_REG ? "core" : "aux"), *addr, count, *buffer);

	if (count == 0)
		return ERROR_OK;

	if (jtag_info->always_check_status_rd)
		CHECK_RETVAL(arc_wait_until_jtag_ready(jtag_info));

	arc_jtag_reset_transaction(jtag_info);

	/* What registers are we writing to? */
	const uint32_t transaction = (type == ARC_JTAG_CORE_REG ?
			ARC_JTAG_WRITE_TO_CORE_REG : ARC_JTAG_WRITE_TO_AUX_REG);
	arc_jtag_set_transaction(jtag_info, transaction, TAP_DRPAUSE);

	for (i = 0; i < count; i++) {
		/* Some of AUX registers are sequential, so we need to set address only
		 * for the first one in sequence. */
		if ( i == 0 || (addr[i] != addr[i-1] + 1) ) {
			arc_jtag_write_ir(jtag_info, ARC_ADDRESS_REG);
			arc_jtag_write_dr(jtag_info, addr[i], TAP_DRPAUSE);
			/* No need to set ir each time, but only if current ir is
			 * different. It is safe to put it into the if body, because this
			 * if is always executed in first iteration. */
			arc_jtag_write_ir(jtag_info, ARC_DATA_REG);
		}
		arc_jtag_write_dr(jtag_info, *(buffer + i), TAP_IDLE);
	}

	uint8_t status_buf[4];
	if (jtag_info->check_status_fl)
		arc_jtag_enque_status_read(jtag_info, status_buf);

	/* Execute queue. */
	CHECK_RETVAL(jtag_execute_queue());
	CHECK_STATUS_FL(jtag_info, status_buf);

	/* Do not advance until write will be finished. This is important in
	 * some situations. For example it is known that at least in some cases
	 * core might hang, if transaction will be reset (via writing NOP to
	 * transaction command register) while it is still being executed by
	 * the core (can happen with long operations like flush of data cache).
	 * */
	if (jtag_info->wait_until_write_finished) {
		CHECK_RETVAL(arc_wait_until_jtag_ready(jtag_info));
	}

	/* Cleanup. */
	arc_jtag_reset_transaction(jtag_info);
	CHECK_RETVAL(jtag_execute_queue());

	return ERROR_OK;
}

int arc_ocd_examine(struct target *target)
{
	uint32_t status;
	struct arc32_common *arc32 = target_to_arc32(target);

	LOG_DEBUG("-");
	CHECK_RETVAL(arc_jtag_startup(&arc32->jtag_info));

	if (!target_was_examined(target)) {
		CHECK_RETVAL(arc_jtag_status(&arc32->jtag_info, &status));
		if (status & ARC_JTAG_STAT_RU) {
			target->state = TARGET_RUNNING;
		} else {
			/* It is first time we examine the target, it is halted
			 * and we don't know why. Let's set debug reason,
			 * otherwise OpenOCD will complain that reason is
			 * unknown. */
			if (target->state == TARGET_UNKNOWN)
				target->debug_reason = DBG_REASON_DBGRQ;
			target->state = TARGET_HALTED;
		}

		/* Read BCRs and configure optional registers. */
		CHECK_RETVAL(arc32_configure(target));

		target_set_examined(target);
	}

	return ERROR_OK;
}

int
OsxUartConvertSettings(
    unsigned int *puRate, 
    unsigned int *puBits, 
    unsigned int *puParity, 
    unsigned int *puStop
    )
{
    int Retval;

    DBG_MSG(DBG_TRACE, "%s\n", __FUNCTION__);

    Retval = OsxUartLookup(*puRate, gBaudTable, COUNTOF(gBaudTable), puRate);
    CHECK_RETVAL(Retval, ExitOnFailure);

    Retval = OsxUartLookup(*puBits, gDataBitsTable, COUNTOF(gDataBitsTable), puBits);
    CHECK_RETVAL(Retval, ExitOnFailure);

    Retval = OsxUartLookup(*puParity, gParityTable, COUNTOF(gParityTable), puParity);
    CHECK_RETVAL(Retval, ExitOnFailure);

    Retval = OsxUartLookup(*puStop, gStopBitsTable, COUNTOF(gStopBitsTable), puStop);
    CHECK_RETVAL(Retval, ExitOnFailure);

ExitOnFailure:

    return Retval;
}

/** Check and if necessary take control of the system
 *
 * \param arm11		Target state variable.
 */
static int arm11_check_init(struct arm11_common *arm11)
{
	CHECK_RETVAL(arm11_read_DSCR(arm11));

	if (!(arm11->dscr & DSCR_HALT_DBG_MODE)) {
		LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr);
		LOG_DEBUG("Bringing target into debug mode");

		arm11->dscr |= DSCR_HALT_DBG_MODE;
		CHECK_RETVAL(arm11_write_DSCR(arm11, arm11->dscr));

		/* add further reset initialization here */

		arm11->simulate_reset_on_next_halt = true;

		if (arm11->dscr & DSCR_CORE_HALTED) {
			/** \todo TODO: this needs further scrutiny because
			  * arm11_debug_entry() never gets called.  (WHY NOT?)
			  * As a result we don't read the actual register states from
			  * the target.
			  */

			arm11->arm.target->state = TARGET_HALTED;
			arm_dpm_report_dscr(arm11->arm.dpm, arm11->dscr);
		} else {
			arm11->arm.target->state = TARGET_RUNNING;
			arm11->arm.target->debug_reason = DBG_REASON_NOTHALTED;
		}

		CHECK_RETVAL(arm11_sc7_clear_vbw(arm11));
	}

	return ERROR_OK;
}

static int arm11_deassert_reset(struct target *target)
{
	struct arm11_common *arm11 = target_to_arm11(target);
	int retval;

	/* be certain SRST is off */
	jtag_add_reset(0, 0);

	/* WORKAROUND i.MX31 problems:  SRST goofs the TAP, and resets
	 * at least DSCR.  OMAP24xx doesn't show that problem, though
	 * SRST-only reset seems to be problematic for other reasons.
	 * (Secure boot sequences being one likelihood!)
	 */
	jtag_add_tlr();

	CHECK_RETVAL(arm11_poll(target));

	if (target->reset_halt) {
		if (target->state != TARGET_HALTED) {
			LOG_WARNING("%s: ran after reset and before halt ...",
					target_name(target));
			if ((retval = target_halt(target)) != ERROR_OK)
				return retval;
		}
	}

	/* maybe restore vector catch config */
	if (target->reset_halt && !(arm11->vcr & 1))
		CHECK_RETVAL(arm11_sc7_set_vcr(arm11, arm11->vcr));

	return ERROR_OK;
}

int arc_ocd_poll(struct target *target)
{
	uint32_t status;
	struct arc32_common *arc32 = target_to_arc32(target);

	/* gdb calls continuously through this arc_poll() function  */
	CHECK_RETVAL(arc_jtag_status(&arc32->jtag_info, &status));

	/* check for processor halted */
	if (status & ARC_JTAG_STAT_RU) {
		target->state = TARGET_RUNNING;
	} else {
		if ((target->state == TARGET_RUNNING) ||
			(target->state == TARGET_RESET)) {

			target->state = TARGET_HALTED;
			LOG_DEBUG("ARC core is halted or in reset.");

			CHECK_RETVAL(arc_dbg_debug_entry(target));

			target_call_event_callbacks(target, TARGET_EVENT_HALTED);
		} else if (target->state == TARGET_DEBUG_RUNNING) {

			target->state = TARGET_HALTED;
			LOG_DEBUG("ARC core is in debug running mode");

			CHECK_RETVAL(arc_dbg_debug_entry(target));

			target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
		}
	}

	return ERROR_OK;
}

int 
BthModCommandMode(
    IN BthMod_T *pMod,
    IN uint16_t  bEnter
    )
{
    int ret;
    char Buf[256];

    /* Attempt to enter command mode */
    ret = UartLineWrite2(pMod->hUart, "$$$", 100, 50);
    CHECK_RETVAL(ret, ExitOnFailure);

    /* Read the response, we should see the cmd prompt */
    ret = UartLineRead(pMod->hUart, Buf, sizeof(Buf), 200);
    if (FAILED(ret) && (ret != E_TIMEOUT))
    {
        CHECK_RETVAL(ret, ExitOnFailure);
    }

    /* Have we entered command mode */
    ret = (SUCCEEDED(ret) && !strncmp(Buf, "CMD", 3)) ? S_OK : E_FAIL;
    CHECK_RETVAL(ret, ExitOnFailure);

ExitOnFailure:

    return ret;
}

int
uInterpStrToBin(
    const char              *pStr,
    unsigned char           *pBuf,
    int                     Len,
    int                     *pLen
    )
{
    int Retval;
    const char *pNext = NULL;
    unsigned long val = 0;
    int i;

    Retval = pStr && pBuf && Len ? UINTERP_OK : UINTERP_EFAIL;
    CHECK_RETVAL(Retval, ExitOnFailure);

    if (pLen)
    {
        *pLen = 0;
    }

    i = 0;

    for ( ; *pStr; )
    {
        /* Skip tokens, treat as white space */
        if (*pStr == '{' || *pStr == '}' || *pStr == ',' || *pStr == ' ' || *pStr == '\t')
        {
            pStr = pStr + 1;
            continue;
        }

        val = uInterpStringToLong(pStr, &pNext, 0);

        /* Did we convert any characters */
        Retval = pStr != pNext ? UINTERP_OK : UINTERP_EFAIL;
        CHECK_RETVAL(Retval, ExitOnFailure);

        /* Are we in byte range */
        Retval = (val <= 255) ? UINTERP_OK : UINTERP_EFAIL;
        CHECK_RETVAL(Retval, ExitOnFailure);

        /* Is there room in the binary buffer */
        Retval = (i < Len) ? UINTERP_OK : UINTERP_EFAIL;
        CHECK_RETVAL(Retval, ExitOnFailure);

        pBuf[i] = (char)val;
        i = i + 1;
        pStr = pNext;
        if (pLen)
        {
            *pLen = *pLen + 1;
        }
    }

ExitOnFailure:

    return Retval;
}

/* target execution control */
static int arm11_halt(struct target *target)
{
	struct arm11_common *arm11 = target_to_arm11(target);

	LOG_DEBUG("target->state: %s",
		target_state_name(target));

	if (target->state == TARGET_UNKNOWN)
	{
		arm11->simulate_reset_on_next_halt = true;
	}

	if (target->state == TARGET_HALTED)
	{
		LOG_DEBUG("target was already halted");
		return ERROR_OK;
	}

	arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);

	CHECK_RETVAL(jtag_execute_queue());

	int i = 0;

	while (1)
	{
		CHECK_RETVAL(arm11_read_DSCR(arm11));

		if (arm11->dscr & DSCR_CORE_HALTED)
			break;


		long long then = 0;
		if (i == 1000)
		{
			then = timeval_ms();
		}
		if (i >= 1000)
		{
			if ((timeval_ms()-then) > 1000)
			{
				LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
				return ERROR_FAIL;
			}
		}
		i++;
	}

	enum target_state old_state	= target->state;

	CHECK_RETVAL(arm11_debug_entry(arm11));

	CHECK_RETVAL(
		target_call_event_callbacks(target,
			old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED));

	return ERROR_OK;
}

int arc_ocd_assert_reset(struct target *target)
{
	struct arc32_common *arc32 = target_to_arc32(target);

	LOG_DEBUG("target->state: %s", target_state_name(target));

	enum reset_types jtag_reset_config = jtag_get_reset_config();

	if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
		/* allow scripts to override the reset event */

		target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
		register_cache_invalidate(arc32->core_cache);
		/* An ARC target might be in halt state after reset, so
		 * if script requested processor to resume, then it must
		 * be manually started to ensure that this request
		 * is satisfied. */
		if (target->state == TARGET_HALTED && !target->reset_halt) {
			/* Resume the target and continue from the current
			 * PC register value. */
			LOG_DEBUG("Starting CPU execution after reset");
			CHECK_RETVAL(target_resume(target, 1, 0, 0, 0));
		}
		target->state = TARGET_RESET;

		return ERROR_OK;
	}

	/* some cores support connecting while srst is asserted
	 * use that mode is it has been configured */

	bool srst_asserted = false;

	if (!(jtag_reset_config & RESET_SRST_PULLS_TRST) &&
			(jtag_reset_config & RESET_SRST_NO_GATING)) {
		jtag_add_reset(0, 1);
		srst_asserted = true;
	}

	if (jtag_reset_config & RESET_HAS_SRST) {
		/* should issue a srst only, but we may have to assert trst as well */
		if (jtag_reset_config & RESET_SRST_PULLS_TRST)
			jtag_add_reset(1, 1);
		else if (!srst_asserted)
			jtag_add_reset(0, 1);
	}

	target->state = TARGET_RESET;
	jtag_add_sleep(50000);

	register_cache_invalidate(arc32->core_cache);

	if (target->reset_halt)
		CHECK_RETVAL(target_halt(target));

	return ERROR_OK;
}

int read_again()
{
	/* tracking files list creation*/
	char *old_list[ntf];
	for(unsigned int i=0; i<ntf; i++){
		old_list[i]=tracked_files[i].logfile;
	}
	

	for(unsigned int i=0; i<ntf; i++){
		if(inotify_rm_watch(inotify_fds[i], inotify_wds[i]) == -1){
			LOG_ERR();
			return -1;
		}
	}
	for(unsigned int i=0; i<ntf; i++){
		if(fclose(tracked_files[i].log_stream)){
			fprintf(core_log, "Cannot close log file \"%s\"\n", tracked_files[i].logfile);
			fflush(core_log);
			return -1;
		}
	}
	free(inotify_fds);
	free(inotify_wds);
	free(fds);
	free(tracked_files);


	int ret;

	ret = parse_config_file((const char *)config_file);
	CHECK_RETVAL(ret);


	ret = init_inotify_actions();
	CHECK_RETVAL(ret);

	init_pollfd_structures();


	/*not good code*/
	ret = create_log_streams(NOTRUNCATE);

	for(unsigned int i=0; i<ntf; i++){
		if(!is_in_list(old_list, tracked_files[i].logfile)){
			if(truncate((const char *)tracked_files[i].logfile, (off_t)0)){
				LOG_ERR();
			}
		}
	}

	CHECK_RETVAL(ret);
	print_starttime_in_new_logfiles();

	return 0;	
}

/**
 * Write a sequence of 4-byte words into target memory.
 *
 * We can write only 4byte words via JTAG, so any non-word writes should be
 * handled at higher levels by read-modify-write.
 *
 * This function writes directly to the memory, leaving any caches (if there
 * are any) in inconsistent state. It is responsibility of upper level to
 * resolve this.
 *
 * @param jtag_info
 * @param addr		Address of first word to write into.
 * @param count		Amount of word to write.
 * @param buffer	Array to write into memory.
 */
int arc_jtag_write_memory(struct arc_jtag *jtag_info, uint32_t addr,
		uint32_t count, const uint32_t* buffer)
{
	assert(jtag_info != NULL);
	assert(buffer != NULL);

	LOG_DEBUG("Writing to memory: addr=0x%08" PRIx32 ";count=%" PRIu32 ";buffer[0]=0x%08" PRIx32,
		addr, count, *buffer);

	/* No need to waste time on useless operations. */
	if (count == 0)
		return ERROR_OK;

	if (jtag_info->always_check_status_rd)
		CHECK_RETVAL(arc_wait_until_jtag_ready(jtag_info));

	/* We do not know where we come from. */
	arc_jtag_reset_transaction(jtag_info);

	/* We want to write to memory. */
	arc_jtag_set_transaction(jtag_info, ARC_JTAG_WRITE_TO_MEMORY, TAP_DRPAUSE);

	/* Set target memory address of the first word. */
	arc_jtag_write_ir(jtag_info, ARC_ADDRESS_REG);
	arc_jtag_write_dr(jtag_info, addr, TAP_DRPAUSE);

	/* Start sending words. Address is auto-incremented on 4bytes by HW. */
	arc_jtag_write_ir(jtag_info, ARC_DATA_REG);
	uint32_t i;
	for (i = 0; i < count; i++) {
		arc_jtag_write_dr(jtag_info, *(buffer + i), TAP_IDLE);
	}

	uint8_t status_buf[4];
	if (jtag_info->check_status_fl)
		arc_jtag_enque_status_read(jtag_info, status_buf);

	/* Run queue. */
	CHECK_RETVAL(jtag_execute_queue());
	CHECK_STATUS_FL(jtag_info, status_buf);

	/* Do not advance until write will be finished. */
	if (jtag_info->wait_until_write_finished) {
		CHECK_RETVAL(arc_wait_until_jtag_ready(jtag_info));
	}

	/* Cleanup. */
	arc_jtag_reset_transaction(jtag_info);
	CHECK_RETVAL(jtag_execute_queue());

	return ERROR_OK;
}

/* talk to the target and set things up */
static int nds32_v3m_examine(struct target *target)
{
	struct nds32_v3m_common *nds32_v3m = target_to_nds32_v3m(target);
	struct nds32 *nds32 = &(nds32_v3m->nds32);
	struct aice_port_s *aice = target_to_aice(target);

	if (!target_was_examined(target)) {
		CHECK_RETVAL(nds32_edm_config(nds32));

		if (nds32->reset_halt_as_examine)
			CHECK_RETVAL(nds32_reset_halt(nds32));
	}

	uint32_t edm_cfg;
	aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CFG, &edm_cfg);

	/* get the number of hardware breakpoints */
	nds32_v3m->n_hbr = (edm_cfg & 0x7) + 1;
	nds32_v3m->used_n_wp = 0;

	/* get the number of hardware watchpoints */
	/* If the WP field is hardwired to zero, it means this is a
	 * simple breakpoint.  Otherwise, if the WP field is writable
	 * then it means this is a regular watchpoints. */
	nds32_v3m->n_hwp = 0;
	for (int32_t i = 0 ; i < nds32_v3m->n_hbr ; i++) {
		/** check the hardware breakpoint is simple or not */
		uint32_t tmp_value;
		aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + i, 0x1);
		aice_read_debug_reg(aice, NDS_EDM_SR_BPC0 + i, &tmp_value);

		if (tmp_value)
			nds32_v3m->n_hwp++;
	}
	/* hardware breakpoint is inserted from high index to low index */
	nds32_v3m->next_hbr_index = nds32_v3m->n_hbr - 1;
	/* hardware watchpoint is inserted from low index to high index */
	nds32_v3m->next_hwp_index = 0;

	LOG_INFO("%s: total hardware breakpoint %d (simple breakpoint %d)",
			target_name(target), nds32_v3m->n_hbr, nds32_v3m->n_hbr - nds32_v3m->n_hwp);
	LOG_INFO("%s: total hardware watchpoint %d", target_name(target), nds32_v3m->n_hwp);

	nds32->target->state = TARGET_RUNNING;
	nds32->target->debug_reason = DBG_REASON_NOTHALTED;

	target_set_examined(target);

	return ERROR_OK;
}

int
BthModSendCommand(
    IN BthMod_T     *pMod,
    IN const char   *pCmd,
    OUT int         *pCmdResult,
    OUT char        *pResponse,
    IN uint16_t     Len
    )
{
    int ret;
    char Buf[256];

    if (pResponse)
    {
        memset(pResponse, 0, Len);
    }
    
    if (pCmdResult)
    {
        *pCmdResult = E_FAIL;
    }

    ret = UartLineWrite(pMod->hUart, pCmd, 100);
    CHECK_RETVAL(ret, ExitOnFailure);

    PortableSleep(250);

    ret = UartLineRead(pMod->hUart, Buf, sizeof(Buf), 100);
    CHECK_RETVAL(ret, ExitOnFailure);

    if (!strncmp(Buf, "AOK", 3))
    {
        if (pResponse)
        {
            strncpy(pResponse, Buf, Len);
        }

        if (pCmdResult)
        {
            *pCmdResult = S_OK;
        }
    }

    ret = UartPurge(pMod->hUart);
    CHECK_RETVAL(ret, ExitOnFailure);

ExitOnFailure:

    return ret;
}

int arc_ocd_examine(struct target *target)
{
	uint32_t status;
	struct arc32_common *arc32 = target_to_arc32(target);

	LOG_DEBUG("-");
	CHECK_RETVAL(arc_jtag_startup(&arc32->jtag_info));

	if (!target_was_examined(target)) {
		/* read ARC core info */
		if (strncmp(target_name(target), ARCEM_STR, 6) == 0) {
			arc32->processor_type = ARCEM_NUM;
			LOG_USER("Processor type: %s", ARCEM_STR);

		} else if (strncmp(target_name(target), ARC600_STR, 6) == 0) {
			arc32->processor_type = ARC600_NUM;
			LOG_USER("Processor type: %s", ARC600_STR);

		} else if (strncmp(target_name(target), ARC700_STR, 6) == 0) {
			arc32->processor_type = ARC700_NUM;
			LOG_USER("Processor type: %s", ARC700_STR);

		} else {
			LOG_WARNING(" THIS IS A UNSUPPORTED TARGET: %s", target_name(target));
		}

		CHECK_RETVAL(arc_jtag_status(&arc32->jtag_info, &status));
		if (status & ARC_JTAG_STAT_RU) {
			target->state = TARGET_RUNNING;
		} else {
			/* It is first time we examine the target, it is halted
			 * and we don't know why. Let's set debug reason,
			 * otherwise OpenOCD will complain that reason is
			 * unknown. */
			if (target->state == TARGET_UNKNOWN)
				target->debug_reason = DBG_REASON_DBGRQ;
			target->state = TARGET_HALTED;
		}

		/* Read BCRs and configure optinal registers. */
		CHECK_RETVAL(arc_regs_read_bcrs(target));
		arc_regs_build_reg_list(target);
		CHECK_RETVAL(arc32_configure(target));

		target_set_examined(target);
	}

	return ERROR_OK;
}