C++ BTIF_READ32函数代码示例

/*****************************************************************************
* FUNCTION
*  hal_btif_is_tx_complete
* DESCRIPTION
*  get tx complete flag
* PARAMETERS
* p_base   [IN]        BTIF module's base address
* RETURNS
*  true means tx complete, false means tx in process
*****************************************************************************/
bool hal_btif_is_tx_complete(P_MTK_BTIF_INFO_STR p_btif)
{
    /*Chaozhong: To be implement*/
    bool b_ret = false;
    unsigned int lsr = 0;
	unsigned long flags = 0;
    unsigned int base = p_btif->base;
	unsigned int tx_empty = 0;
	unsigned int rx_dr = 0;
	unsigned int tx_irq_disable = 0;
	/*3 conditions allow clock to be disable
	1. if TEMT is set or not
	2. if DR is set or not
	3. Tx IRQ is disabled or not*/
    lsr = BTIF_READ32(BTIF_LSR(base));
	tx_empty = lsr & BTIF_LSR_TEMT_BIT;
	rx_dr = lsr & BTIF_LSR_DR_BIT;
	tx_irq_disable = BTIF_READ32(BTIF_IER(base)) & BTIF_IER_TXEEN;
	
    b_ret = (tx_empty && (0 == tx_irq_disable) && (0 == rx_dr) ) ? true : false;
	if (!b_ret)
	{
	    BTIF_DBG_FUNC("BTIF flag, tx_empty:%d, rx_dr:%d, tx_irq_disable:%d\n", tx_empty, rx_dr, tx_irq_disable);
	}
 #if NEW_TX_HANDLING_SUPPORT
    spin_lock_irqsave(&(p_btif->tx_fifo_spinlock), flags);
	/*clear Tx enable flag if necessary*/
	if (!(kfifo_is_empty(p_btif->p_tx_fifo))){
		BTIF_DBG_FUNC("BTIF tx FIFO is not empty\n");
		b_ret = false;
	}
	spin_unlock_irqrestore(&(p_btif->tx_fifo_spinlock), flags);
#endif
    return b_ret;
}

int btif_rx_dma_ctrl(P_MTK_DMA_INFO_STR p_dma_info, ENUM_DMA_CTRL ctrl_id)
{
	unsigned int i_ret = -1;
	unsigned long base = p_dma_info->base;
	unsigned int dat;

	BTIF_TRC_FUNC();

	if (DMA_CTRL_DISABLE == ctrl_id) {
		/*if write 0 to EN bit, DMA will be stoped imediately*/
		/*if write 1 to STOP bit, DMA will be stoped after current transaction finished*/
		/*BTIF_CLR_BIT(RX_DMA_EN(base), DMA_EN_BIT);*/
		BTIF_SET_BIT(RX_DMA_STOP(base), DMA_STOP_BIT);
		do {
			dat = BTIF_READ32(RX_DMA_STOP(base));
		} while (0x1 & dat);
		BTIF_DBG_FUNC("BTIF Rx DMA disabled,EN(0x%x),STOP(0x%x)\n",
			BTIF_READ32(RX_DMA_EN(base)), BTIF_READ32(RX_DMA_STOP(base)));
		i_ret = 0;
	} else if (DMA_CTRL_ENABLE == ctrl_id) {
		BTIF_SET_BIT(RX_DMA_EN(base), DMA_EN_BIT);
		BTIF_DBG_FUNC("BTIF Rx DMA enabled\n");
		i_ret = 0;
	} else {
/*TODO: print error log*/
		BTIF_ERR_FUNC("invalid DMA ctrl_id (%d)\n", ctrl_id);
		i_ret = ERR_INVALID_PAR;
	}
	BTIF_TRC_FUNC();

	return i_ret;
}

int hal_btif_dma_hw_init(P_MTK_DMA_INFO_STR p_dma_info)
{
	int i_ret = 0;
	unsigned long base = p_dma_info->base;
	P_DMA_VFIFO p_vfifo = p_dma_info->p_vfifo;
	P_MTK_BTIF_DMA_VFIFO p_mtk_dma_vfifo = container_of(p_vfifo,
							    MTK_BTIF_DMA_VFIFO,
							    vfifo);

	if (DMA_DIR_RX == p_dma_info->dir) {
/*Rx DMA*/
/*do hardware reset*/
//		BTIF_SET_BIT(RX_DMA_RST(base), DMA_HARD_RST);
//		BTIF_CLR_BIT(RX_DMA_RST(base), DMA_HARD_RST);
		
		BTIF_SET_BIT(RX_DMA_RST(base), DMA_WARM_RST);
		while((0x01 & BTIF_READ32(RX_DMA_EN(base))));
/*write vfifo base address to VFF_ADDR*/
		btif_reg_sync_writel(p_vfifo->phy_addr, RX_DMA_VFF_ADDR(base));
/*write vfifo length to VFF_LEN*/
		btif_reg_sync_writel(p_vfifo->vfifo_size, RX_DMA_VFF_LEN(base));
/*write wpt to VFF_WPT*/
		btif_reg_sync_writel(p_mtk_dma_vfifo->wpt,
				     RX_DMA_VFF_WPT(base));
		btif_reg_sync_writel(p_mtk_dma_vfifo->rpt,
					 RX_DMA_VFF_RPT(base));
/*write vff_thre to VFF_THRESHOLD*/
		btif_reg_sync_writel(p_vfifo->thre, RX_DMA_VFF_THRE(base));
/*clear Rx DMA's interrupt status*/
		BTIF_SET_BIT(RX_DMA_INT_FLAG(base),
			     RX_DMA_INT_DONE | RX_DMA_INT_THRE);

/*enable Rx IER by default*/
		btif_rx_dma_ier_ctrl(p_dma_info, true);
	} else {
/*Tx DMA*/
/*do hardware reset*/
//		BTIF_SET_BIT(TX_DMA_RST(base), DMA_HARD_RST);
//		BTIF_CLR_BIT(TX_DMA_RST(base), DMA_HARD_RST);
		BTIF_SET_BIT(TX_DMA_RST(base), DMA_WARM_RST);
		while((0x01 & BTIF_READ32(TX_DMA_EN(base))));
/*write vfifo base address to VFF_ADDR*/
		btif_reg_sync_writel(p_vfifo->phy_addr, TX_DMA_VFF_ADDR(base));
/*write vfifo length to VFF_LEN*/
		btif_reg_sync_writel(p_vfifo->vfifo_size, TX_DMA_VFF_LEN(base));
/*write wpt to VFF_WPT*/
		btif_reg_sync_writel(p_mtk_dma_vfifo->wpt,
				     TX_DMA_VFF_WPT(base));
		btif_reg_sync_writel(p_mtk_dma_vfifo->rpt,
				     TX_DMA_VFF_RPT(base));
/*write vff_thre to VFF_THRESHOLD*/
		btif_reg_sync_writel(p_vfifo->thre, TX_DMA_VFF_THRE(base));

		BTIF_CLR_BIT(TX_DMA_INT_FLAG(base), TX_DMA_INT_FLAG_MASK);

		hal_btif_dma_ier_ctrl(p_dma_info, false);
	}

	return i_ret;
}

/*****************************************************************************
* FUNCTION
*  hal_btif_rx_handler
* DESCRIPTION
*  lower level interrupt handler
* PARAMETERS
* p_base   [IN]        BTIF module's base address
* p_buf     [IN/OUT] pointer to rx data buffer
* max_len  [IN]        max length of rx buffer
* RETURNS
*  0 means success; negative means fail; positive means rx data length
*****************************************************************************/
int hal_btif_irq_handler(P_MTK_BTIF_INFO_STR p_btif,
                         unsigned char *p_buf, const unsigned int max_len)
{
    /*Chaozhong: To be implement*/
    int i_ret = -1;
    unsigned int iir = 0;
    unsigned int rx_len = 0;
    unsigned int base = p_btif->base;
    unsigned long irq_flag = 0;

#if 0
    /*check parameter valid or not*/
    if ((NULL == p_buf) || (max_len == 0)) {
        i_ret = ERR_INVALID_PAR;
        return i_ret;
    }
#endif
    spin_lock_irqsave(&(g_clk_cg_spinlock), irq_flag);
#if MTK_BTIF_ENABLE_CLK_CTL
    if (0 == clock_is_on(MTK_BTIF_CG_BIT)) {
        spin_unlock_irqrestore(&(g_clk_cg_spinlock), irq_flag);
        BTIF_ERR_FUNC("%s: clock is off before irq handle done!!!\n",
                      __FILE__);
        return i_ret;
    }
#endif
    /*read interrupt identifier register*/
    iir = BTIF_READ32(BTIF_IIR(base));

    /*is rx interrupt exist?*/
#if 0
    while ((iir & BTIF_IIR_RX) && (rx_len < max_len)) {
        rx_len +=
            btif_rx_irq_handler(p_btif, (p_buf + rx_len),
                                (max_len - rx_len));

        /*update IIR*/
        iir = BTIF_READ32(BTIF_IIR(base));
    }
#endif

    while (iir & (BTIF_IIR_RX | BTIF_IIR_RX_TIMEOUT)) {
        rx_len += btif_rx_irq_handler(p_btif, p_buf, max_len);

        /*update IIR*/
        iir = BTIF_READ32(BTIF_IIR(base));
    }

    /*is tx interrupt exist?*/
    if (iir & BTIF_IIR_TX_EMPTY) {
        i_ret = btif_tx_irq_handler(p_btif);
    }
    spin_unlock_irqrestore(&(g_clk_cg_spinlock), irq_flag);
    i_ret = rx_len != 0 ? rx_len : i_ret;
    return i_ret;
}

/*****************************************************************************
* FUNCTION
*  btif_rx_irq_handler
* DESCRIPTION
*  lower level rx interrupt handler
* PARAMETERS
* p_base   [IN]        BTIF module's base address
* RETURNS
*  positive means length of rx data , negative means fail
*****************************************************************************/
static int btif_rx_irq_handler(P_MTK_BTIF_INFO_STR p_btif_info,
                               unsigned char *p_buf, const unsigned int max_len)
{
    /*Chaozhong: To be implement*/
    int i_ret = 0;
    unsigned int iir = 0;
    unsigned int rx_len = 0;
    unsigned int base = p_btif_info->base;
    unsigned char rx_buf[256];
    unsigned int local_buf_len = 256;
    btif_rx_buf_write rx_cb = p_btif_info->rx_cb;
    unsigned int total_len = 0;

    /*read interrupt identifier register*/
    iir = BTIF_READ32(BTIF_IIR(base));
    while ((iir & (BTIF_IIR_RX | BTIF_IIR_RX_TIMEOUT)) &&
            (rx_len < local_buf_len)) {
        rx_buf[rx_len] = BTIF_READ8(base);
        rx_len++;
        /*need to consult CC Hwang for advice */
        /*whether we need to do memory barrier here
        Ans: no
        */
        /*whether we need to d memory barrier when call BTIF_SET_BIT or BTIF_CLR_BIT
        Ans: no
        */
        if (rx_len == local_buf_len) {
            if (rx_cb)
                (*rx_cb) (p_btif_info, rx_buf, rx_len);
            rx_len = 0;
            total_len += rx_len;
        }
        iir = BTIF_READ32(BTIF_IIR(base));
    }
    total_len += rx_len;
    if (rx_len && rx_cb)
        (*rx_cb) (p_btif_info, rx_buf, rx_len);

    /*make sure all data write back to memory, mb or dsb?
    need to consult CC Hwang for advice
    Ans: no need here
    */
    i_ret = total_len;
    return i_ret;
}

/*****************************************************************************
* FUNCTION
*  btif_tx_irq_handler
* DESCRIPTION
*  lower level tx interrupt handler 
* PARAMETERS
* p_base   [IN]        BTIF module's base address
* p_buf     [IN/OUT] pointer to rx data buffer
* max_len  [IN]        max length of rx buffer
* RETURNS
*  0 means success, negative means fail
*****************************************************************************/
static int btif_tx_irq_handler (P_MTK_BTIF_INFO_STR p_btif)
{
    int i_ret = -1;
#if NEW_TX_HANDLING_SUPPORT
    int how_many = 0;
    unsigned int lsr;
	unsigned int ava_len = 0;
	unsigned int base = p_btif->base;
	char local_buf[BTIF_TX_FIFO_SIZE];
	char *p_data = local_buf;
	unsigned long flag = 0;
	
    struct kfifo *p_tx_fifo = p_btif->p_tx_fifo;
	
	/*read LSR and check THER or TEMT, either one is 1 means can accept tx data*/
	lsr = BTIF_READ32(BTIF_LSR(base));
	
	if (lsr & BTIF_LSR_TEMT_BIT)
	{
		/*Tx Holding Register if empty, which means we can write tx FIFO count to BTIF*/
		ava_len = BTIF_TX_FIFO_SIZE;
	}
	else if (lsr & BTIF_LSR_THRE_BIT)
	{
		/*Tx Holding Register if empty, which means we can write (Tx FIFO count - Tx threshold)to BTIF*/
		ava_len = BTIF_TX_FIFO_SIZE - BTIF_TX_FIFO_THRE;
	}else
	{
		/*this means data size in tx FIFO is more than Tx threshold, we will not write data to THR*/
		ava_len = 0;
		goto ret;
	}
	spin_lock_irqsave(&(p_btif->tx_fifo_spinlock), flag);
	how_many = kfifo_out(p_tx_fifo, local_buf, ava_len);
	spin_unlock_irqrestore(&(p_btif->tx_fifo_spinlock), flag);
	BTIF_DBG_FUNC("BTIF tx size %d done, left:%d\n", how_many, kfifo_avail(p_tx_fifo));
    while (how_many--)
    {
        btif_reg_sync_writeb(*(p_data++), BTIF_THR(base));
    }
	
	spin_lock_irqsave(&(p_btif->tx_fifo_spinlock), flag);
	/*clear Tx enable flag if necessary*/
	if (kfifo_is_empty(p_tx_fifo)){
        hal_btif_tx_ier_ctrl(p_btif, false);
		BTIF_DBG_FUNC("BTIF tx FIFO is empty\n");
	}
	spin_unlock_irqrestore(&(p_btif->tx_fifo_spinlock), flag);
ret:
#else
    /*clear Tx enable flag*/
    hal_btif_tx_ier_ctrl(p_btif, false);
#endif
    i_ret = 0;
    return i_ret;
}

/*****************************************************************************
* FUNCTION
*  hal_btif_is_tx_allow
* DESCRIPTION
*  whether tx is allowed
* PARAMETERS
* p_base   [IN]        BTIF module's base address
* RETURNS
* true if tx operation is allowed; false if tx is not allowed
*****************************************************************************/
bool hal_btif_is_tx_allow(P_MTK_BTIF_INFO_STR p_btif)
{
#define MIN_TX_MB ((26 * 1000000 / 13) / 1000000 )
#define AVE_TX_MB ((26 * 1000000 / 8) / 1000000 )

    /*Chaozhong: To be implement*/
    bool b_ret = false;
    unsigned int base = p_btif->base;
    unsigned int lsr = 0;
    unsigned int wait_us = (BTIF_TX_FIFO_SIZE - BTIF_TX_FIFO_THRE) / MIN_TX_MB ; /*only ava length */
#if NEW_TX_HANDLING_SUPPORT
    unsigned long flags = 0;
    spin_lock_irqsave(&(p_btif->tx_fifo_spinlock), flags);
	/*clear Tx enable flag if necessary*/
	if (kfifo_is_full(p_btif->p_tx_fifo)){
		BTIF_WARN_FUNC("BTIF tx FIFO is full\n");
		b_ret = false;
	}
	else
	{
	    b_ret = true;
	}
	spin_unlock_irqrestore(&(p_btif->tx_fifo_spinlock), flags);
#else
    /*read LSR and check THER or TEMT, either one is 1 means can accept tx data*/
    lsr = BTIF_READ32(BTIF_LSR(base));
    
    if(!(lsr & (BTIF_LSR_TEMT_BIT | BTIF_LSR_THRE_BIT)))
    {
        BTIF_DBG_FUNC("wait for %d ~ %d us\n", wait_us, 3 * wait_us);
        //usleep_range(wait_us, 3 * 10 * wait_us);
        usleep_range(wait_us, 3 * wait_us);
    }
    lsr = BTIF_READ32(BTIF_LSR(base));
    b_ret = (lsr & (BTIF_LSR_TEMT_BIT | BTIF_LSR_THRE_BIT)) ? true : false;
    if (!b_ret)
        BTIF_DBG_FUNC(" tx is not allowed for the moment\n");
    else
        BTIF_DBG_FUNC(" tx is allowed\n");
#endif	
    return b_ret;
}

static bool _btif_is_tx_allow(P_MTK_BTIF_INFO_STR p_btif)
{
    /*Chaozhong: To be implement*/
    bool b_ret = false;
    unsigned int base = p_btif->base;
    unsigned int lsr = 0;

    /*read LSR and check THER or TEMT, either one is 1 means can accept tx data*/
    lsr = BTIF_READ32(BTIF_LSR(base));
    b_ret = (lsr & (BTIF_LSR_TEMT_BIT | BTIF_LSR_THRE_BIT)) ? true : false;
    return b_ret;
}

static int _is_tx_dma_in_flush(P_MTK_DMA_INFO_STR p_dma_info)
{
	bool b_ret = true;
	unsigned int base = p_dma_info->base;

/*see if flush operation is in process*/
	b_ret =
	    ((DMA_FLUSH_BIT & BTIF_READ32(TX_DMA_FLUSH(base))) !=
	     0) ? true : false;

	return b_ret;
}

/*****************************************************************************
* FUNCTION
*  hal_dma_get_ava_room
* DESCRIPTION
*  get tx available room
* PARAMETERS
* p_dma_info   [IN]        pointer to BTIF dma channel's information
* RETURNS
*  available room  size
*****************************************************************************/
int hal_dma_get_ava_room(P_MTK_DMA_INFO_STR p_dma_info)
{
	int i_ret = -1;
	unsigned long base = p_dma_info->base;

/*read vFIFO's left size*/
	i_ret = BTIF_READ32(TX_DMA_VFF_LEFT_SIZE(base));
	BTIF_DBG_FUNC("DMA tx ava room (%d).\n", i_ret);
	if (0 == i_ret)
		BTIF_INFO_FUNC("DMA tx vfifo is full.\n");

	return i_ret;
}

/*****************************************************************************
* FUNCTION
*  hal_dma_is_tx_complete
* DESCRIPTION
*  get tx complete flag
* PARAMETERS
* p_dma_info   [IN]        pointer to BTIF dma channel's information
* RETURNS
*  true means tx complete, false means tx in process
*****************************************************************************/
bool hal_dma_is_tx_complete(P_MTK_DMA_INFO_STR p_dma_info)
{
	bool b_ret = -1;
	unsigned int base = p_dma_info->base;
	unsigned int valid_size = BTIF_READ32(TX_DMA_VFF_VALID_SIZE(base));
	unsigned int inter_size = BTIF_READ32(TX_DMA_INT_BUF_SIZE(base));
	unsigned int tx_done = is_tx_dma_irq_finish_done(p_dma_info);

/*only when virtual FIFO valid size and Tx channel internal buffer size are both becomes to be 0,
we can identify tx operation finished
confirmed with DE.
*/
	if ((0 == valid_size) && (0 == inter_size) && (1 == tx_done)) {
		b_ret = true;
		BTIF_DBG_FUNC("DMA tx finished.\n");
	} else {
		BTIF_DBG_FUNC
		    ("DMA tx is in process. vfifo valid size(%d), dma internal size (%d), tx_done(%d)\n",
		     valid_size, inter_size, tx_done);
		b_ret = false;
	}

	return b_ret;
}

static int _tx_dma_flush(P_MTK_DMA_INFO_STR p_dma_info)
{
	unsigned int i_ret = -1;
	unsigned long base = p_dma_info->base;
	unsigned int stop = BTIF_READ32(TX_DMA_STOP(base));

/*in MTK DMA BTIF channel we cannot set STOP and FLUSH bit at the same time*/
	if ((DMA_STOP_BIT && stop) != 0)
		BTIF_ERR_FUNC("BTIF's DMA in stop state, omit flush operation\n");
	else {
		BTIF_DBG_FUNC("flush tx dma\n");
		BTIF_SET_BIT(TX_DMA_FLUSH(base), DMA_FLUSH_BIT);
		i_ret = 0;
	}
	return i_ret;
}

static int btif_tx_thr_set(P_MTK_BTIF_INFO_STR p_btif, unsigned int thr_count)
{
    int i_ret = -1;
    unsigned int base = p_btif->base;
    unsigned int value = 0;

    /*read BTIF_TRI_LVL*/
    value = BTIF_READ32(BTIF_TRI_LVL(base));
    /*clear Tx threshold bits*/
    value &= (~BTIF_TRI_LVL_TX_MASK);
    /*set tx threshold bits*/
    value |= BTIF_TRI_LVL_TX(BTIF_TX_FIFO_THRE);
    /*write back to BTIF_TRI_LVL*/
    btif_reg_sync_writel(value, BTIF_TRI_LVL(base));

    return i_ret;
}

static int is_tx_dma_irq_finish_done(P_MTK_DMA_INFO_STR p_dma_info)
{
	int tx_irq_done = 0;
#if MTK_BTIF_ENABLE_CLK_REF_COUNTER
/*if we enable this clock reference couner, just return , because when enter IRQ handler, DMA's clock will be opened*/
	tx_irq_done = 1;
#else
	unsigned long flag = 0;
	unsigned int base = p_dma_info->base;
	spin_lock_irqsave(&(g_clk_cg_spinlock), flag);
	tx_irq_done =
	    (0 ==
	     (BTIF_READ32(TX_DMA_INT_FLAG(base)) &
	      TX_DMA_INT_FLAG_MASK)) ? 1 : 0;
	spin_unlock_irqrestore(&(g_clk_cg_spinlock), flag);
#endif
	return tx_irq_done;
}

/*****************************************************************************
* FUNCTION
*  hal_rx_dma_irq_handler
* DESCRIPTION
*  lower level rx interrupt handler
* PARAMETERS
* p_dma_info   [IN]        pointer to BTIF dma channel's information
* p_buf     [IN/OUT] pointer to rx data buffer
* max_len  [IN]        max length of rx buffer
* RETURNS
*  0 means success, negative means fail
*****************************************************************************/
int hal_rx_dma_irq_handler(P_MTK_DMA_INFO_STR p_dma_info,
			   unsigned char *p_buf, const unsigned int max_len)
{
	int i_ret = -1;
	unsigned int valid_len = 0;
	unsigned int wpt_wrap = 0;
	unsigned int rpt_wrap = 0;
	unsigned int wpt = 0;
	unsigned int rpt = 0;
	unsigned int tail_len = 0;
	unsigned int real_len = 0;
	unsigned int base = p_dma_info->base;
	P_DMA_VFIFO p_vfifo = p_dma_info->p_vfifo;
	dma_rx_buf_write rx_cb = p_dma_info->rx_cb;
	unsigned char *p_vff_buf = NULL;
	unsigned char *vff_base = p_vfifo->p_vir_addr;
	unsigned int vff_size = p_vfifo->vfifo_size;
	P_MTK_BTIF_DMA_VFIFO p_mtk_vfifo = container_of(p_vfifo,
							MTK_BTIF_DMA_VFIFO,
							vfifo);
	unsigned long flag = 0;

	spin_lock_irqsave(&(g_clk_cg_spinlock), flag);
	if (0 == clock_is_on(MTK_BTIF_APDMA_CLK_CG)) {
		spin_unlock_irqrestore(&(g_clk_cg_spinlock), flag);
		BTIF_ERR_FUNC("%s: clock is off before irq handle done!!!\n",
			      __FILE__);
		return i_ret;
	}
/*disable DMA Rx IER*/
	hal_btif_dma_ier_ctrl(p_dma_info, false);

/*clear Rx DMA's interrupt status*/
	BTIF_SET_BIT(RX_DMA_INT_FLAG(base), RX_DMA_INT_DONE | RX_DMA_INT_THRE);

	valid_len = BTIF_READ32(RX_DMA_VFF_VALID_SIZE(base));
	rpt = BTIF_READ32(RX_DMA_VFF_RPT(base));
	wpt = BTIF_READ32(RX_DMA_VFF_WPT(base));
	if ((0 == valid_len) && (rpt == wpt)) {
		BTIF_DBG_FUNC
		    ("rx interrupt, no data available in Rx DMA, wpt(0x%08x), rpt(0x%08x)\n",
		     rpt, wpt);
	}

	i_ret = 0;

	while ((0 < valid_len) || (rpt != wpt)) {
		rpt_wrap = rpt & DMA_RPT_WRAP;
		wpt_wrap = wpt & DMA_WPT_WRAP;
		rpt &= DMA_RPT_MASK;
		wpt &= DMA_WPT_MASK;

/*calcaute length of available data  in vFIFO*/
		if (wpt_wrap != p_mtk_vfifo->last_wpt_wrap) {
			real_len = wpt + vff_size - rpt;
		} else {
			real_len = wpt - rpt;
		}

		if (NULL != rx_cb) {
			tail_len = vff_size - rpt;
			p_vff_buf = vff_base + rpt;
			if (tail_len >= real_len) {
				(*rx_cb) (p_dma_info, p_vff_buf, real_len);
			} else {
				(*rx_cb) (p_dma_info, p_vff_buf, tail_len);
				p_vff_buf = vff_base;
				(*rx_cb) (p_dma_info, p_vff_buf, real_len -
					  tail_len);
			}
			i_ret += real_len;
		} else {
			BTIF_ERR_FUNC
			    ("no rx_cb found, please check your init process\n");
		}
		dsb();
		rpt += real_len;
		if (rpt >= vff_size) {
/*read wrap bit should be revert*/
			rpt_wrap ^= DMA_RPT_WRAP;
			rpt %= vff_size;
		}
		rpt |= rpt_wrap;
/*record wpt, last_wpt_wrap, rpt, last_rpt_wrap*/
		p_mtk_vfifo->wpt = wpt;
		p_mtk_vfifo->last_wpt_wrap = wpt_wrap;

		p_mtk_vfifo->rpt = rpt;
//.........这里部分代码省略.........