本文整理汇总了C++中ATA_OUTL函数的典型用法代码示例。如果您正苦于以下问题:C++ ATA_OUTL函数的具体用法?C++ ATA_OUTL怎么用?C++ ATA_OUTL使用的例子?那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。
在下文中一共展示了ATA_OUTL函数的15个代码示例,这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞,您的评价将有助于系统推荐出更棒的C++代码示例。
示例1: ahci_em_setleds
static void
ahci_em_setleds(device_t dev, int c)
{
struct ahci_enclosure *enc;
int timeout;
int16_t val;
enc = device_get_softc(dev);
val = 0;
if (enc->status[c][2] & 0x80) /* Activity */
val |= (1 << 0);
if (enc->status[c][2] & SESCTL_RQSID) /* Identification */
val |= (1 << 3);
else if (enc->status[c][3] & SESCTL_RQSFLT) /* Fault */
val |= (1 << 6);
else if (enc->status[c][1] & 0x02) /* Rebuild */
val |= (1 << 6) | (1 << 3);
timeout = 10000;
while (ATA_INL(enc->r_memc, 0) & (AHCI_EM_TM | AHCI_EM_RST) &&
--timeout > 0)
DELAY(100);
if (timeout == 0)
device_printf(dev, "Transmit timeout\n");
ATA_OUTL(enc->r_memt, 0, (1 << 8) | (0 << 16) | (0 << 24));
ATA_OUTL(enc->r_memt, 4, c | (0 << 8) | (val << 16));
ATA_OUTL(enc->r_memc, 0, AHCI_EM_TM);
}
示例2: ata_nvidia_chipinit
static int
ata_nvidia_chipinit(device_t dev)
{
struct ata_pci_controller *ctlr = device_get_softc(dev);
if (ata_setup_interrupt(dev, ata_generic_intr))
return ENXIO;
if (ctlr->chip->cfg1 & NVAHCI) {
ctlr->ch_attach = ata_nvidia_ch_attach_dumb;
ctlr->setmode = ata_sata_setmode;
} else if (ctlr->chip->max_dma >= ATA_SA150) {
if (pci_read_config(dev, PCIR_BAR(5), 1) & 1)
ctlr->r_type2 = SYS_RES_IOPORT;
else
ctlr->r_type2 = SYS_RES_MEMORY;
ctlr->r_rid2 = PCIR_BAR(5);
if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
&ctlr->r_rid2, RF_ACTIVE))) {
int offset = ctlr->chip->cfg1 & NV4 ? 0x0440 : 0x0010;
ctlr->ch_attach = ata_nvidia_ch_attach;
ctlr->ch_detach = ata_pci_ch_detach;
ctlr->reset = ata_nvidia_reset;
/* enable control access */
pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) | 0x04,1);
/* MCP55 seems to need some time to allow r_res2 read. */
DELAY(10);
if (ctlr->chip->cfg1 & NVQ) {
/* clear interrupt status */
ATA_OUTL(ctlr->r_res2, offset, 0x00ff00ff);
/* enable device and PHY state change interrupts */
ATA_OUTL(ctlr->r_res2, offset + 4, 0x000d000d);
/* disable NCQ support */
ATA_OUTL(ctlr->r_res2, 0x0400,
ATA_INL(ctlr->r_res2, 0x0400) & 0xfffffff9);
}
else {
/* clear interrupt status */
ATA_OUTB(ctlr->r_res2, offset, 0xff);
/* enable device and PHY state change interrupts */
ATA_OUTB(ctlr->r_res2, offset + 1, 0xdd);
}
}
ctlr->setmode = ata_sata_setmode;
ctlr->getrev = ata_sata_getrev;
}
else {
/* disable prefetch, postwrite */
pci_write_config(dev, 0x51, pci_read_config(dev, 0x51, 1) & 0x0f, 1);
ctlr->setmode = ata_nvidia_setmode;
}
return 0;
}
示例3: imx6_ahci_phy_write
static int
imx6_ahci_phy_write(struct ahci_controller* sc, uint32_t addr,
uint16_t data)
{
int error;
error = imx6_ahci_phy_addr(sc, addr);
if (error != 0) {
device_printf(sc->dev, "%s: error on imx6_ahci_phy_addr\n",
__FUNCTION__);
return (error);
}
ATA_OUTL(sc->r_mem, SATA_P0PHYCR, data);
error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_CAP_DATA, true);
if (error != 0) {
device_printf(sc->dev,
"%s: error on SATA_P0PHYCR_CR_CAP_DATA=1\n", __FUNCTION__);
return (error);
}
if (imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_CAP_DATA, false) != 0) {
device_printf(sc->dev,
"%s: error on SATA_P0PHYCR_CR_CAP_DATA=0\n", __FUNCTION__);
return (error);
}
if ((addr == SATA_PHY_CLOCK_RESET) && data) {
/* we can't check ACK after RESET */
ATA_OUTL(sc->r_mem, SATA_P0PHYCR,
SATA_P0PHYCR_CR_DATA_IN(data) | SATA_P0PHYCR_CR_WRITE);
return (0);
}
error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_WRITE, true);
if (error != 0) {
device_printf(sc->dev, "%s: error on SATA_P0PHYCR_CR_WRITE=1\n",
__FUNCTION__);
return (error);
}
error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_WRITE, false);
if (error != 0) {
device_printf(sc->dev, "%s: error on SATA_P0PHYCR_CR_WRITE=0\n",
__FUNCTION__);
return (error);
}
return (0);
}
示例4: ata_nvidia_status
static int
ata_nvidia_status(device_t dev)
{
struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
struct ata_channel *ch = device_get_softc(dev);
int offset = ctlr->chip->cfg1 & NV4 ? 0x0440 : 0x0010;
int shift = ch->unit << (ctlr->chip->cfg1 & NVQ ? 4 : 2);
u_int32_t istatus;
/* get interrupt status */
if (ctlr->chip->cfg1 & NVQ)
istatus = ATA_INL(ctlr->r_res2, offset);
else
istatus = ATA_INB(ctlr->r_res2, offset);
/* do we have any PHY events ? */
if (istatus & (0x0c << shift))
ata_sata_phy_check_events(dev, -1);
/* clear interrupt(s) */
if (ctlr->chip->cfg1 & NVQ)
ATA_OUTL(ctlr->r_res2, offset, (0x0f << shift) | 0x00f000f0);
else
ATA_OUTB(ctlr->r_res2, offset, (0x0f << shift));
/* do we have any device action ? */
return (istatus & (0x01 << shift));
}
示例5: imx6_ahci_phy_ctrl
static int
imx6_ahci_phy_ctrl(struct ahci_controller* sc, uint32_t bitmask, bool on)
{
uint32_t v;
int timeout;
bool state;
v = ATA_INL(sc->r_mem, SATA_P0PHYCR);
if (on) {
v |= bitmask;
} else {
v &= ~bitmask;
}
ATA_OUTL(sc->r_mem, SATA_P0PHYCR, v);
for (timeout = 5000; timeout > 0; --timeout) {
v = ATA_INL(sc->r_mem, SATA_P0PHYSR);
state = (v & SATA_P0PHYSR_CR_ACK) == SATA_P0PHYSR_CR_ACK;
if(state == on) {
break;
}
DELAY(100);
}
if (timeout > 0) {
return (0);
}
return (ETIMEDOUT);
}
示例6: imx6_ahci_phy_addr
static int
imx6_ahci_phy_addr(struct ahci_controller* sc, uint32_t addr)
{
int error;
DELAY(100);
ATA_OUTL(sc->r_mem, SATA_P0PHYCR, addr);
error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_CAP_ADDR, true);
if (error != 0) {
device_printf(sc->dev,
"%s: timeout on SATA_P0PHYCR_CR_CAP_ADDR=1\n",
__FUNCTION__);
return (error);
}
error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_CAP_ADDR, false);
if (error != 0) {
device_printf(sc->dev,
"%s: timeout on SATA_P0PHYCR_CR_CAP_ADDR=0\n",
__FUNCTION__);
return (error);
}
return (0);
}
示例7: ahci_clr
static void inline
ahci_clr(struct resource *m, bus_size_t off, uint32_t clr)
{
uint32_t val = ATA_INL(m, off);
val &= ~clr;
ATA_OUTL(m, off, val);
}
示例8: ahci_set
static void inline
ahci_set(struct resource *m, bus_size_t off, uint32_t set)
{
uint32_t val = ATA_INL(m, off);
val |= set;
ATA_OUTL(m, off, val);
}
示例9: mvs_suspend
static int
mvs_suspend(device_t dev)
{
struct mvs_controller *ctlr = device_get_softc(dev);
bus_generic_suspend(dev);
/* Mask chip interrupts */
ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, 0x00000000);
return 0;
}
示例10: ata_sii_ch_attach
static int
ata_sii_ch_attach(device_t dev)
{
struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
struct ata_channel *ch = device_get_softc(dev);
int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
int i;
for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
ch->r_io[i].res = ctlr->r_res2;
ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8);
}
ch->r_io[ATA_CONTROL].res = ctlr->r_res2;
ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8);
ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
ata_default_registers(dev);
ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2;
ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8);
ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2;
ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8);
ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2;
ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8);
if (ctlr->chip->max_dma >= ATA_SA150) {
ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8);
ch->r_io[ATA_SERROR].res = ctlr->r_res2;
ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8);
ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8);
ch->flags |= ATA_NO_SLAVE;
ch->flags |= ATA_SATA;
ch->flags |= ATA_KNOWN_PRESENCE;
/* enable PHY state change interrupt */
ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16));
}
if (ctlr->chip->cfg2 & SII_BUG) {
/* work around errata in early chips */
ch->dma.boundary = 8192;
ch->dma.segsize = 15 * DEV_BSIZE;
}
ata_pci_hw(dev);
ch->hw.status = ata_sii_status;
if (ctlr->chip->cfg2 & SII_SETCLK)
ch->flags |= ATA_CHECKS_CABLE;
ata_pci_dmainit(dev);
return 0;
}
示例11: tegra_ahci_suspend
static int
tegra_ahci_suspend(device_t dev)
{
struct tegra_ahci_sc *sc = device_get_softc(dev);
bus_generic_suspend(dev);
/* Disable interupts, so the state change(s) doesn't trigger. */
ATA_OUTL(sc->ctlr.r_mem, AHCI_GHC,
ATA_INL(sc->ctlr.r_mem, AHCI_GHC) & (~AHCI_GHC_IE));
return (0);
}
示例12: mvs_ctlr_setup
static int
mvs_ctlr_setup(device_t dev)
{
struct mvs_controller *ctlr = device_get_softc(dev);
int ccc = ctlr->ccc, cccc = ctlr->cccc, ccim = 0;
/* Mask chip interrupts */
ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, 0x00000000);
/* Clear HC interrupts */
ATA_OUTL(ctlr->r_mem, HC_IC, 0x00000000);
/* Clear chip interrupts */
ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIC, 0);
/* Configure per-HC CCC */
if (ccc && bootverbose) {
device_printf(dev,
"CCC with %dus/%dcmd enabled\n",
ctlr->ccc, ctlr->cccc);
}
ccc *= 150;
ATA_OUTL(ctlr->r_mem, HC_ICT, cccc);
ATA_OUTL(ctlr->r_mem, HC_ITT, ccc);
if (ccc)
ccim |= IC_HC0_COAL_DONE;
/* Enable chip interrupts */
ctlr->gmim = ((ccc ? IC_HC0_COAL_DONE :
(IC_DONE_HC0 & CHIP_SOC_HC0_MASK(ctlr->channels))) |
(IC_ERR_HC0 & CHIP_SOC_HC0_MASK(ctlr->channels)));
ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, ctlr->gmim | ctlr->pmim);
return (0);
}
示例13: ahci_a10_ch_start
static void
ahci_a10_ch_start(struct ahci_channel *ch)
{
uint32_t reg;
/*
* Magical values from Allwinner SDK, setup the DMA before start
* operations on this channel.
*/
reg = ATA_INL(ch->r_mem, AHCI_P0DMACR);
reg &= ~0xff00;
reg |= 0x4400;
ATA_OUTL(ch->r_mem, AHCI_P0DMACR, reg);
}
示例14: ata_siiprb_issue_cmd
static int
ata_siiprb_issue_cmd(device_t dev)
{
struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
struct ata_channel *ch = device_get_softc(dev);
u_int64_t prb_bus = ch->dma.work_bus;
u_int32_t status;
int offset = ch->unit * 0x2000;
int timeout;
bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_PREWRITE);
/* issue command to chip */
ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus);
ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus >> 32);
/* poll for command finished */
for (timeout = 0; timeout < 10000; timeout++) {
DELAY(1000);
if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000)
break;
}
bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_POSTWRITE);
// SOS XXX ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x00010000);
ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x08ff08ff);
if (timeout >= 1000)
return EIO;
if (bootverbose)
device_printf(dev, "siiprb_issue_cmd time=%dms status=%08x\n",
timeout, status);
return 0;
}
示例15: mvs_edma
static void
mvs_edma(device_t dev, device_t child, int mode)
{
struct mvs_controller *ctlr = device_get_softc(dev);
int unit = ((struct mvs_channel *)device_get_softc(child))->unit;
int bit = IC_DONE_IRQ << (unit * 2);
if (ctlr->ccc == 0)
return;
/* CCC is not working for non-EDMA mode. Unmask device interrupts. */
mtx_lock(&ctlr->mtx);
if (mode == MVS_EDMA_OFF)
ctlr->pmim |= bit;
else
ctlr->pmim &= ~bit;
ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, ctlr->gmim | ctlr->pmim);
mtx_unlock(&ctlr->mtx);
}