C++ AT91_SMC_TDF_函数代码示例

static void afeb9260_nand_hw_init(void)
{
	unsigned long csa;

	/* Enable CS3 */
	csa = at91_sys_read(AT91_MATRIX_EBICSA);
	at91_sys_write(AT91_MATRIX_EBICSA,
		       csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);

	/* Configure SMC CS3 for NAND/SmartMedia */
	at91_sys_write(AT91_SMC_SETUP(3),
		       AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
		       AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
	at91_sys_write(AT91_SMC_PULSE(3),
		       AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
		       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
	at91_sys_write(AT91_SMC_CYCLE(3),
		       AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
	at91_sys_write(AT91_SMC_MODE(3),
		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
		       AT91_SMC_EXNWMODE_DISABLE |
		       AT91_SMC_DBW_8 |
		       AT91_SMC_TDF_(2));

	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);

	/* Configure RDY/BSY */
	at91_set_gpio_input(AT91_PIN_PC13, 1);

	/* Enable NandFlash */
	at91_set_gpio_output(AT91_PIN_PC14, 1);
}

static void __init sam9_smc_cs_configure(void __iomem *base, struct sam9_smc_config* config)
{

	/* Setup register */
	__raw_writel(AT91_SMC_NWESETUP_(config->nwe_setup)
		   | AT91_SMC_NCS_WRSETUP_(config->ncs_write_setup)
		   | AT91_SMC_NRDSETUP_(config->nrd_setup)
		   | AT91_SMC_NCS_RDSETUP_(config->ncs_read_setup),
		   base + AT91_SMC_SETUP);

	/* Pulse register */
	__raw_writel(AT91_SMC_NWEPULSE_(config->nwe_pulse)
		   | AT91_SMC_NCS_WRPULSE_(config->ncs_write_pulse)
		   | AT91_SMC_NRDPULSE_(config->nrd_pulse)
		   | AT91_SMC_NCS_RDPULSE_(config->ncs_read_pulse),
		   base + AT91_SMC_PULSE);

	/* Cycle register */
	__raw_writel(AT91_SMC_NWECYCLE_(config->write_cycle)
		   | AT91_SMC_NRDCYCLE_(config->read_cycle),
		   base + AT91_SMC_CYCLE);

	/* Mode register */
	__raw_writel(config->mode
		   | AT91_SMC_TDF_(config->tdf_cycles),
		   base + AT91_SMC_MODE);
}

static void set_smc_timings(const u8 chipselect, const u16 cycle,
			    const u16 setup, const u16 pulse,
			    const u16 data_float, int use_iordy)
{
	unsigned long mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
			     AT91_SMC_BAT_SELECT;

	/* disable or enable waiting for IORDY signal */
	if (use_iordy)
		mode |= AT91_SMC_EXNWMODE_READY;

	/* add data float cycles if needed */
	if (data_float)
		mode |= AT91_SMC_TDF_(data_float);

	at91_sys_write(AT91_SMC_MODE(chipselect), mode);

	/* setup timings in SMC */
	at91_sys_write(AT91_SMC_SETUP(chipselect), AT91_SMC_NWESETUP_(setup) |
						   AT91_SMC_NCS_WRSETUP_(0) |
						   AT91_SMC_NRDSETUP_(setup) |
						   AT91_SMC_NCS_RDSETUP_(0));
	at91_sys_write(AT91_SMC_PULSE(chipselect), AT91_SMC_NWEPULSE_(pulse) |
						   AT91_SMC_NCS_WRPULSE_(cycle) |
						   AT91_SMC_NRDPULSE_(pulse) |
						   AT91_SMC_NCS_RDPULSE_(cycle));
	at91_sys_write(AT91_SMC_CYCLE(chipselect), AT91_SMC_NWECYCLE_(cycle) |
						   AT91_SMC_NRDCYCLE_(cycle));
}

static void __init eco920_board_init(void)
{
	/* DBGU on ttyS0. (Rx & Tx only */
	at91_register_uart(0, 0, 0);
	at91_add_device_serial();
	at91_add_device_eth(&eco920_eth_data);
	at91_add_device_usbh(&eco920_usbh_data);
	at91_add_device_udc(&eco920_udc_data);

	at91_add_device_mci(0, &eco920_mci0_data);
	platform_device_register(&eco920_flash);

	at91_ramc_write(0, AT91_SMC_CSR(7),	AT91_SMC_RWHOLD_(1)
				| AT91_SMC_RWSETUP_(1)
				| AT91_SMC_DBW_8
				| AT91_SMC_WSEN
				| AT91_SMC_NWS_(15));

	at91_set_A_periph(AT91_PIN_PC6, 1);

	at91_set_gpio_input(AT91_PIN_PA23, 0);
	at91_set_deglitch(AT91_PIN_PA23, 1);

/* Initialization of the Static Memory Controller for Chip Select 3 */
	at91_ramc_write(0, AT91_SMC_CSR(3),
		AT91_SMC_DBW_16  |	/* 16 bit */
		AT91_SMC_WSEN    |
		AT91_SMC_NWS_(5) |	/* wait states */
		AT91_SMC_TDF_(1)	/* float time */
	);

	at91_add_device_spi(eco920_spi_devices, ARRAY_SIZE(eco920_spi_devices));
	/* LEDs */
	at91_gpio_leds(eco920_leds, ARRAY_SIZE(eco920_leds));
}

static void yl9200_init_video(void)
{
	/* NWAIT Signal */
	at91_set_A_periph(AT91_PIN_PC6, 0);

	/* Initialization of the Static Memory Controller for Chip Select 2 */
	at91_ramc_write(0, AT91_SMC_CSR(2), AT91_SMC_DBW_16		/* 16 bit */
			| AT91_SMC_WSEN | AT91_SMC_NWS_(0x4)	/* wait states */
			| AT91_SMC_TDF_(0x100)			/* float time */
	);
}

static void __init ek_init_video(void)
{
	/* NWAIT Signal */
	at91_set_A_periph(AT91_PIN_PC6, 0);

	/* Initialization of the Static Memory Controller for Chip Select 3 */
	at91_sys_write(AT91_SMC_CSR(3), AT91_SMC_DBW_16			/* 16 bit */
				| AT91_SMC_WSEN | AT91_SMC_NWS_(5)	/* wait states */
				| AT91_SMC_TDF_(1)			/* float time */
	);

	at91_ics1523_init();
}

void init_smc_ddr()
{
#if 0
	printf("leds should change now!\n");
  	at91_set_gpio_output(AT91_PIN_PA0, 1);
	at91_set_gpio_output(AT91_PIN_PA1, 0);

	vTaskDelay(2000);
	printf("leds should change now!\n");
	at91_set_gpio_value(AT91_PIN_PA0, 0);
	at91_set_gpio_value(AT91_PIN_PA1, 1);
#endif
  
/* Configure the EBI1 pins for the wr switch */
	int i;
	
	/* PC16..31: periphA as EBI1_D16..31 */
	for (i = AT91_PIN_PC16; i <= AT91_PIN_PC31; i++){
		at91_set_A_periph(i, 0);
	}
	/* PC2 and PC3 too: EBI1_A19 EBI1_A20 */
	at91_set_A_periph(AT91_PIN_PC2, 0);
	at91_set_A_periph(AT91_PIN_PC3, 0);
	
	
	/* FIXME: We should pull rst high for when it is programmed */

	/* Then, write the EBI1 configuration (NCS0 == 0x1000.0000) */
	at91_sys_write(AT91_SMC_SETUP(0),
				AT91_SMC_NWESETUP_(4) |
				AT91_SMC_NCS_WRSETUP_(2) |
				AT91_SMC_NRDSETUP_(4) |
				AT91_SMC_NCS_RDSETUP_(2));
	at91_sys_write(AT91_SMC_PULSE(0),
				AT91_SMC_NWEPULSE_(30) |
				AT91_SMC_NCS_WRPULSE_(34) |
				AT91_SMC_NRDPULSE_(30) |
				AT91_SMC_NCS_RDPULSE_(34));
	at91_sys_write(AT91_SMC_CYCLE(0),
				AT91_SMC_NWECYCLE_(40) |
				AT91_SMC_NRDCYCLE_(40));
	at91_sys_write(AT91_SMC_MODE(0),
				AT91_SMC_DBW_32 |
				AT91_SMC_TDF_(0) |
				AT91_SMC_READMODE |
				AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_FROZEN);
	

	
	
}

void nandflash_hw_init(void)
{
	unsigned int reg;

	/* Configure nand pins */
	const struct pio_desc nand_pins_lo[] = {
		{"NANDOE",	AT91C_PIN_PD(0), 0,		PIO_PULLUP, PIO_PERIPH_A},
		{"NANDWE",	AT91C_PIN_PD(1), 0,		PIO_PULLUP, PIO_PERIPH_A},
		{"NANDALE",	AT91C_PIN_PD(2), 0,		PIO_PULLUP, PIO_PERIPH_A},
		{"NANDCLE",	AT91C_PIN_PD(3), 0,		PIO_PULLUP, PIO_PERIPH_A},
		{"NANDCS",	CONFIG_SYS_NAND_ENABLE_PIN,	1, PIO_PULLUP, PIO_OUTPUT},
		{(char *)0,	0, 0, PIO_DEFAULT, PIO_PERIPH_A},
	};

	reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA);
	reg |= AT91C_EBI_CS3A_SM;

	reg &= ~AT91C_EBI_NFD0_ON_D16;	/* nandflash connect to D0~D15 */

	reg |= AT91C_EBI_DRV;	/* according to IAR verification package */
	writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA);

	/* Configure SMC CS3 */
	writel((AT91C_SMC_NWESETUP_(1)
		| AT91C_SMC_NCS_WRSETUP_(0)
		| AT91C_SMC_NRDSETUP_(3)
		| AT91C_SMC_NCS_RDSETUP_(0)), 
		AT91C_BASE_SMC + SMC_SETUP3);

	writel((AT91C_SMC_NWEPULSE_(3)
		| AT91C_SMC_NCS_WRPULSE_(5) 
		| AT91C_SMC_NRDPULSE_(4) 
		| AT91C_SMC_NCS_RDPULSE_(6)), 
		AT91C_BASE_SMC + SMC_PULSE3);

	writel((AT91C_SMC_NWECYCLE_(5)
		| AT91C_SMC_NRDCYCLE_(8)),
		AT91C_BASE_SMC + SMC_CYCLE3);

	writel((AT91C_SMC_READMODE 
		| AT91C_SMC_WRITEMODE 
		| AT91C_SMC_NWAITM_NWAIT_DISABLE 
		| AT91C_SMC_DBW_WIDTH_BITS_8
		| AT91_SMC_TDF_(1)), 
		AT91C_BASE_SMC + SMC_CTRL3);

	/* Configure the nand controller pins*/
	writel((1 << AT91C_ID_PIOC_D), (PMC_PCER + AT91C_BASE_PMC));
	pio_configure(nand_pins_lo);
}

static void __init yl_9200_init_video(void)
{
	at91_sys_write(AT91_PIOC + PIO_ASR,AT91_PIN_PC6);
	at91_sys_write(AT91_PIOC + PIO_BSR,0);
	at91_sys_write(AT91_PIOC + PIO_ASR,AT91_PIN_PC6);

	at91_sys_write( AT91_SMC_CSR(2),
	AT91_SMC_NWS_(0x4) |
	AT91_SMC_WSEN |
	AT91_SMC_TDF_(0x100) |
	AT91_SMC_DBW
	);



}

void nandflash_hw_init(void)
{
	unsigned int reg;

	/* Setup Smart Media, first enable the address range of
	 * CS3 in HMATRIX user interface  */
	reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA);
	reg |= AT91C_EBI_CS3A_SM;
	writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA);

	/* Configure SMC CS3 */
	writel((AT91C_SMC_NWESETUP_(1)
		| AT91C_SMC_NCS_WRSETUP_(0)
		| AT91C_SMC_NRDSETUP_(1)
		| AT91C_SMC_NCS_RDSETUP_(0)),
		AT91C_BASE_SMC + SMC_SETUP3);

	writel((AT91C_SMC_NWEPULSE_(3)
		| AT91C_SMC_NCS_WRPULSE_(3)
		| AT91C_SMC_NRDPULSE_(3)
		| AT91C_SMC_NCS_RDPULSE_(3)),
		AT91C_BASE_SMC + SMC_PULSE3);

	writel((AT91C_SMC_NWECYCLE_(5)
		| AT91C_SMC_NRDCYCLE_(5)),
		AT91C_BASE_SMC + SMC_CYCLE3);

	writel((AT91C_SMC_READMODE
		| AT91C_SMC_WRITEMODE
		/* AT91C_SMC_NWAITM_NWAIT_DISABLE */
		| (0x0 << 5)
		| AT91C_SMC_DBW_WIDTH_BITS_16
		| AT91_SMC_TDF_(2)),
		AT91C_BASE_SMC + SMC_CTRL3);

	/* configure NAND pins */

	/* {"NANDCS", AT91C_PIN_PC(14), 1, PIO_PULLUP, PIO_OUTPUT} */
	writel((0x01 << 14), AT91C_BASE_PIOC + PIO_IDR(0));
	writel((0x01 << 14), AT91C_BASE_PIOC + PIO_PPUDR(0));
	writel((0x01 << 14), AT91C_BASE_PIOC + PIO_SODR(0));
	writel((0x01 << 14), AT91C_BASE_PIOC + PIO_OER(0));
	writel((0x01 << 14), AT91C_BASE_PIOC + PIO_PER(0));

	/* enable PIOC clock  */
	writel((1 << AT91C_ID_PIOC), PMC_PCER + AT91C_BASE_PMC);
}

void nandflash_hw_init(void)
{
	unsigned int reg;

	/* Configure PIOs */
	const struct pio_desc nand_pins[] = {
		{"NANDCS",	CONFIG_SYS_NAND_ENABLE_PIN,	1, PIO_PULLUP, PIO_OUTPUT},
		{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
	};

	/* Setup Smart Media, first enable the address range of CS3
	 * in HMATRIX user interface
	* EBI IO in 1.8V mode */
	reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA);
	reg |= AT91C_EBI_CS3A_SM;
	reg &= ~AT91C_VDDIOM_SEL_33V;
	writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA);

	/* Configure SMC CS3 */
	writel((AT91C_SMC_NWESETUP_(2)
		| AT91C_SMC_NCS_WRSETUP_(0)
		| AT91C_SMC_NRDSETUP_(2)
		| AT91C_SMC_NCS_RDSETUP_(0)),
		AT91C_BASE_SMC + SMC_SETUP3);

	writel((AT91C_SMC_NWEPULSE_(4)
		| AT91C_SMC_NCS_WRPULSE_(4)
		| AT91C_SMC_NRDPULSE_(4)
		| AT91C_SMC_NCS_RDPULSE_(4)),
		AT91C_BASE_SMC + SMC_PULSE3);

	writel((AT91C_SMC_NWECYCLE_(7)
		|  AT91C_SMC_NRDCYCLE_(7)),
		AT91C_BASE_SMC + SMC_CYCLE3);

	writel((AT91C_SMC_READMODE
		| AT91C_SMC_WRITEMODE
		| AT91C_SMC_NWAITM_NWAIT_DISABLE
		| AT91C_SMC_DBW_WIDTH_BITS_16
		| AT91_SMC_TDF_(3)),
		AT91C_BASE_SMC + SMC_CTRL3);

	/* Configure the PIO controll */
	writel((1 << AT91C_ID_PIOC), (PMC_PCER + AT91C_BASE_PMC));
	pio_configure(nand_pins);

}

void nandflash_hw_init(void)
{
	unsigned int reg;

	/* Configure NANDFlash pins*/
	const struct pio_desc nand_pins[] = {
		{"NANDALE",	AT91C_PIN_PB(2),		0, PIO_PULLUP, PIO_PERIPH_A},
		{"NANDCLE",	AT91C_PIN_PB(3),		0, PIO_PULLUP, PIO_PERIPH_A},
		{"NANDOE",	AT91C_PIN_PB(4),		0, PIO_PULLUP, PIO_PERIPH_A},
		{"NANDWE",	AT91C_PIN_PB(5),		0, PIO_PULLUP, PIO_PERIPH_A},
		{"NANDCS",	CONFIG_SYS_NAND_ENABLE_PIN,	1, PIO_PULLUP, PIO_OUTPUT},
		{(char *)0, 	0, 0, PIO_DEFAULT, PIO_PERIPH_A},
	};

	/* Setup Smart Media, first enable the address range of CS3 in HMATRIX user interface  */
	reg = readl(AT91C_BASE_CCFG + CCFG_EBI0CSA);
	reg |= AT91C_EBI_CS3A_SM;
	writel(reg, AT91C_BASE_CCFG + CCFG_EBI0CSA);

	/* Configure SMC CS3 */
	writel((AT91C_SMC_NWESETUP_(1)
		| AT91C_SMC_NCS_WRSETUP_(0)
		| AT91C_SMC_NRDSETUP_(1)
		| AT91C_SMC_NCS_RDSETUP_(0)),
		AT91C_BASE_SMC + SMC_SETUP3);

	writel((AT91C_SMC_NWEPULSE_(3)
		| AT91C_SMC_NCS_WRPULSE_(3)
		| AT91C_SMC_NRDPULSE_(3)
		| AT91C_SMC_NCS_RDPULSE_(3)),
		AT91C_BASE_SMC + SMC_PULSE3);

	writel((AT91C_SMC_NWECYCLE_(5)
		|  AT91C_SMC_NRDCYCLE_(5)),
		AT91C_BASE_SMC + SMC_CYCLE3);

	writel((AT91C_SMC_READMODE
		| AT91C_SMC_WRITEMODE
		| AT91C_SMC_NWAITM_NWAIT_DISABLE
		| AT91C_SMC_DBW_WIDTH_BITS_8
		| AT91_SMC_TDF_(2)),
		AT91C_BASE_SMC + SMC_CTRL3);

	/* Configure the NANDFlash pins */
	pmc_enable_periph_clock(AT91C_ID_PIOB);
	pio_configure(nand_pins);
}

/*
 * Enable NAND and detect card.
 */
static void at91_nand_enable(struct at91_nand_host *host)
{
	unsigned int csa;

	/* Setup Smart Media, first enable the address range of CS3 */
	csa = at91_sys_read(AT91_EBI_CSA);
	at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);

	/* set the bus interface characteristics */
	at91_sys_write(AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN
				| AT91_SMC_NWS_(5)
				| AT91_SMC_TDF_(1)
				| AT91_SMC_RWSETUP_(0)	/* tDS Data Set up Time 30 - ns */
				| AT91_SMC_RWHOLD_(1)	/* tDH Data Hold Time 20 - ns */
	);

	if (host->board->enable_pin)
		at91_set_gpio_value(host->board->enable_pin, 0);
}

/*
 * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT
 * controller debugging
 * The ET1100 is located at physical address 0x70000000
 * Its process memory is located at physical address 0x70001000
 */
static void meesc_ethercat_hw_init(void)
{
	/* Configure SMC EBI1_CS0 for EtherCAT */
	at91_sys_write(AT91_SMC1_SETUP(0),
		AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
		AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
	at91_sys_write(AT91_SMC1_PULSE(0),
		AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(9) |
		AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(9));
	at91_sys_write(AT91_SMC1_CYCLE(0),
		AT91_SMC_NWECYCLE_(10) | AT91_SMC_NRDCYCLE_(5));
	/* Configure behavior at external wait signal, byte-select mode, 16 bit
	data bus width, none data float wait states and TDF optimization */
	at91_sys_write(AT91_SMC1_MODE(0),
		AT91_SMC_READMODE | AT91_SMC_EXNWMODE_READY |
		AT91_SMC_BAT_SELECT | AT91_SMC_DBW_16 | AT91_SMC_TDF_(0) |
		AT91_SMC_TDFMODE);

	/* Configure RDY/BSY */
	at91_set_B_periph(AT91_PIN_PE20, 0);	/* EBI1_NWAIT */
}

static void at91cap9_nor_hw_init(void)
{
    unsigned long csa;

    /* Ensure EBI supply is 3.3V */
    csa = at91_sys_read(AT91_MATRIX_EBICSA);
    at91_sys_write(AT91_MATRIX_EBICSA,
                   csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
    /* Configure SMC CS0 for parallel flash */
    at91_sys_write(AT91_SMC_SETUP(0),
                   AT91_SMC_NWESETUP_(4) | AT91_SMC_NCS_WRSETUP_(2) |
                   AT91_SMC_NRDSETUP_(4) | AT91_SMC_NCS_RDSETUP_(2));
    at91_sys_write(AT91_SMC_PULSE(0),
                   AT91_SMC_NWEPULSE_(8) | AT91_SMC_NCS_WRPULSE_(10) |
                   AT91_SMC_NRDPULSE_(8) | AT91_SMC_NCS_RDPULSE_(10));
    at91_sys_write(AT91_SMC_CYCLE(0),
                   AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
    at91_sys_write(AT91_SMC_MODE(0),
                   AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
                   AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE |
                   AT91_SMC_DBW_16 | AT91_SMC_TDF_(1));
}