C++ AGESA_TESTPOINT函数代码示例

AGESA_STATUS
MemRecNMemInitML (
  IN OUT   MEM_NB_BLOCK *NBPtr
  )
{
  AGESA_STATUS Status;
  MEM_TECH_BLOCK *TechPtr;

  TechPtr = NBPtr->TechPtr;

  Status = AGESA_FATAL;
  if (TechPtr->DimmPresence (TechPtr)) {

    if (MemRecNAutoConfigNb (NBPtr)) {

      AGESA_TESTPOINT (TpProcMemPlatformSpecificConfig, &(NBPtr->MemPtr->StdHeader));
      if (MemRecNPlatformSpecML (NBPtr)) {
        AgesaHookBeforeDramInitRecovery (0, NBPtr->MemPtr);
        AGESA_TESTPOINT (TpProcMemStartDcts, &(NBPtr->MemPtr->StdHeader));
        MemRecNStartupDCTML (NBPtr);

        AGESA_TESTPOINT (TpProcMemMtrrConfiguration, &(NBPtr->MemPtr->StdHeader));
        MemRecNCPUMemRecTypingNb (NBPtr);

        AGESA_TESTPOINT (TpProcMemDramTraining, &(NBPtr->MemPtr->StdHeader));
        NBPtr->TrainingFlow (NBPtr);

        Status = AGESA_SUCCESS;
      }
    }
  }

  return Status;
}

/**
 *
 *
 *      This function returns the conditional MSR device register list according
 *      to the register list ID.
 *
 *      @param[in]       *Device - pointer to the CONDITIONAL_PCI_DEVICE_DESCRIPTOR
 *      @param[out]      **RegisterHdr - pointer to the address of the register list
 *      @param[in]       *StdHeader - Config handle for library and services
 *
 *      @return          AGESA_STATUS
 *                          - AGESA_ALERT
 *                          - AGESA_FATAL
 *                          - AGESA_SUCCESS
 *                          - AGESA_WARNING
 */
AGESA_STATUS
MemFS3GetCMsrDeviceRegisterList (
  IN       CONDITIONAL_MSR_DEVICE_DESCRIPTOR     *Device,
     OUT   CMSR_REGISTER_BLOCK_HEADER            **RegisterHdr,
  IN       AMD_CONFIG_PARAMS                     *StdHeader
  )
{
  AGESA_STATUS RetVal;
  S3_MEM_NB_BLOCK *S3NBPtr;
  VOID *RegisterHeader;
  LOCATE_HEAP_PTR LocHeap;
  AGESA_BUFFER_PARAMS LocBufferParams;

  LibAmdMemCopy (&LocBufferParams.StdHeader, StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader);
  LocHeap.BufferHandle = AMD_MEM_S3_NB_HANDLE;
  LocBufferParams.BufferHandle = AMD_MEM_S3_NB_HANDLE;


  AGESA_TESTPOINT (TpIfBeforeLocateS3CMsrBuffer, StdHeader);
  if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) {
    S3NBPtr = (S3_MEM_NB_BLOCK *)LocHeap.BufferPtr;
  } else {
    ASSERT(FALSE) ; // No match for heap status, but could not locate "AMD_MEM_S3_NB_HANDLE" in heap for S3GetMsr
    return AGESA_FATAL;
  }
  AGESA_TESTPOINT (TpIfAfterLocateS3CMsrBuffer, StdHeader);

  // NB block has already been constructed by main block.
  // No need to construct it here.
  RetVal = S3NBPtr[BSP_DIE].MemS3GetDeviceRegLst (Device->RegisterListID, &RegisterHeader);
  *RegisterHdr = (CMSR_REGISTER_BLOCK_HEADER *)RegisterHeader;
  return RetVal;
}

/**
 * Topology Services Initialization.
 *
 * Build the system topology data structures.  Initialize hardware values needed
 * for correct fabric operation, such as core count.
 *
 * @param[in]   StdHeader              Opaque handle to standard config header
 * @param[in]   PlatformConfiguration  The platform configuration options.
 *
 * @retval      AGESA_SUCCESS     Only information events logged.
 *
 */
AGESA_STATUS
AmdTopologyInitialize (
  IN       AMD_CONFIG_PARAMS      *StdHeader,
  IN       PLATFORM_CONFIGURATION *PlatformConfiguration
  )
{
  STATE_DATA State;
  NORTHBRIDGE Nb;

  State.ConfigHandle = StdHeader;
  State.PlatformConfiguration = PlatformConfiguration;

  // Initialize for status and event output
  State.MaxEventClass = AGESA_SUCCESS;

  // Allocate permanent heap structs that are interfaces to other AGESA services.
  NewNodeAndSocketTables (&State);

  if (IsBootCore (&State)) {
    AGESA_TESTPOINT (TpProcTopologyEntry, State.ConfigHandle);
    // Create the BSP's northbridge.
    NewNorthBridge (0, &State, &Nb);
    State.Nb = &Nb;

    CoherentInit (&State);
    AGESA_TESTPOINT (TpProcTopologyDone, State.ConfigHandle);
  } else {
    // Do the AP Topology Init, which produces Node and Socket Maps for the AP's use.
    NewNorthBridge (0, &State, &Nb);
    State.Nb = &Nb;
    InitApMaps (&State);
  }
  return State.MaxEventClass;
}

VOID
AmdMemInitDataStructDef (
  IN OUT   MEM_DATA_STRUCT *MemPtr,
  IN OUT   PLATFORM_CONFIGURATION   *PlatFormConfig
  )
{
  UINT8 p;
  UINT8 i;
  // We need a way of specifying default values for each particular northbridge
  // family.  We also need to make sure that the IBV knows which parameter struct
  // is for which northbridge.
  //----------------------------------------------------------------------------
  AGESA_TESTPOINT (TpProcMemBeforeMemDataInit, &MemPtr->StdHeader);

  MemPtr->PlatFormConfig = PlatFormConfig;

  memNBInstalled[0].MemNInitDefaults (MemPtr);

  //----------------------------------------------------------------------------
  // INITIALIZE PLATFORM SPECIFIC CONFIGURATION STRUCT
  //----------------------------------------------------------------------------
  AGESA_TESTPOINT (TpProcMemPlatformSpecificConfig, &MemPtr->StdHeader);
  i = 0;
  for (p = 0; p < MAX_PLATFORM_TYPES; p++) {
    if (memPlatformTypeInstalled[i] != NULL) {
      MemPtr->GetPlatformCfg[p] = memPlatformTypeInstalled[i];
      i++;
    } else {
      MemPtr->GetPlatformCfg[p] = MemAGetPsCfgDef;
    }
  }
  AGESA_TESTPOINT (TpProcMemAfterMemDataInit, &MemPtr->StdHeader);
  MemPtr->ErrorHandling = MemErrHandle;
}

/**
 * Application Processor perform a function as directed by the BSC.
 *
 * This is needed for an AP task that must run after AGESA has relinquished control
 * of the APs to the IBV.
 *
 * @param[in]     AmdApExeParams  The interface struct for any required routine.
 *
 * @return        The most severe AGESA_STATUS returned by any called service.  Note
 *                that this will be the return value passed back to the BSC as the
 *                return value for the call out.
 *
 */
AGESA_STATUS
AmdLateRunApTask (
  IN       AP_EXE_PARAMS  *AmdApExeParams
  )
{
  AGESA_STATUS        CalledAgesaStatus;
  AGESA_STATUS        ApLateTaskStatus;
  DISPATCH_TABLE      *Entry;

  AGESA_TESTPOINT (TpIfAmdLateRunApTaskEntry, &AmdApExeParams->StdHeader);

  ASSERT (AmdApExeParams != NULL);
  ApLateTaskStatus = AGESA_SUCCESS;
  CalledAgesaStatus = AGESA_UNSUPPORTED;

  // Dispatch, if valid
  Entry = (DISPATCH_TABLE *) ApDispatchTable;
  while (Entry->FunctionId != 0) {
    if (AmdApExeParams->FunctionNumber == Entry->FunctionId) {
      CalledAgesaStatus = Entry->EntryPoint (AmdApExeParams);
      break;
    }
    Entry++;
  }

  if (CalledAgesaStatus > ApLateTaskStatus) {
    ApLateTaskStatus = CalledAgesaStatus;
  }

  AGESA_TESTPOINT (TpIfAmdLateRunApTaskExit, &AmdApExeParams->StdHeader);
  return  ApLateTaskStatus;
}

/**
 * Optimize Link Features.
 *
 * Based on Link capabilities, apply optimization rules to come up with the best
 * settings, including several external limit decision from the interface. This includes
 * handling of subLinks.  Finally, after the port list data is updated, set the hardware
 * state for all Links.
 *
 * @param[in] State our global state
 */
VOID
STATIC
LinkOptimization (
  IN       STATE_DATA *State
  )
{
  AGESA_TESTPOINT (TpProcHtOptGather, State->ConfigHandle);
  State->HtFeatures->GatherLinkData (State);

  AGESA_TESTPOINT (TpProcHtOptRegang, State->ConfigHandle);
  State->HtFeatures->RegangLinks (State);

  AGESA_TESTPOINT (TpProcHtOptLinks, State->ConfigHandle);
  State->HtFeatures->SelectOptimalWidthAndFrequency (State);

  // A likely cause of mixed Retry settings on coherent links is sublink ratio balancing
  // so check this after doing the sublinks.
  AGESA_TESTPOINT (TpProcHtOptSubLinks, State->ConfigHandle);
  State->HtFeatures->SubLinkRatioFixup (State);
  if (State->HtFeatures->IsCoherentRetryFixup (State)) {
    // Fix sublinks again within HT1 only frequencies, as ratios may be invalid again.
    State->HtFeatures->SubLinkRatioFixup (State);
  }

  AGESA_TESTPOINT (TpProcHtOptFinish, State->ConfigHandle);
  State->HtFeatures->SetLinkData (State);
}

/**
 * Main entry point for the AMD_S3LATE_RESTORE function.
 *
 * This entry point is responsible for restoring saved registers and preparing the
 * silicon components for OS restart.
 *
 * @param[in,out] S3LateParams   Required input parameters for the AMD_S3LATE_RESTORE
 *                                  entry point.
 *
 * @return        Aggregated status across all internal AMD S3 late restore calls invoked.
 *
 */
AGESA_STATUS
AmdS3LateRestore (
  IN OUT   AMD_S3LATE_PARAMS *S3LateParams
  )
{
  UINT8  *BufferPointer;
  VOID   *OrMaskPtr;
  VOID   *LateContextPtr;
  AGESA_STATUS ReturnStatus;
  AGESA_STATUS CalledStatus;

  AGESA_TESTPOINT (TpIfAmdS3LateRestoreEntry, &S3LateParams->StdHeader);
  IDS_HDT_CONSOLE (MAIN_FLOW, "AmdS3LateRestore: Start\n\n");
  ReturnStatus = AGESA_SUCCESS;

  ASSERT (S3LateParams != NULL);

  BufferPointer = (UINT8 *) S3LateParams->S3DataBlock.VolatileStorage;
  S3LateParams->StdHeader.HeapBasePtr = &BufferPointer[((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->HeapOffset];
  ASSERT (S3LateParams->StdHeader.HeapBasePtr != NULL);

  IDS_OPTION_HOOK (IDS_PLATFORMCFG_OVERRIDE, &S3LateParams->PlatformConfig, &S3LateParams->StdHeader);
  IDS_OPTION_HOOK (IDS_BEFORE_S3_RESTORE, S3LateParams, &(S3LateParams->StdHeader));

  if (((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->RegisterDataSize != 0) {
    LateContextPtr = &BufferPointer[((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->RegisterDataOffset];
    // Restore registers before exiting self refresh
    RestorePreESRContext (&OrMaskPtr,
                          LateContextPtr,
                          S3_LATE_RESTORE,
                          &S3LateParams->StdHeader);
    // Restore registers after exiting self refresh
    RestorePostESRContext (OrMaskPtr,
                           LateContextPtr,
                           S3_LATE_RESTORE,
                           &S3LateParams->StdHeader);
  }

  // Dispatch any features needing to run at this time point
  IDS_HDT_CONSOLE (CPU_TRACE, "  Dispatch CPU features at S3 late restore end\n");
  CalledStatus = DispatchCpuFeatures (CPU_FEAT_S3_LATE_RESTORE_END,
                                      &S3LateParams->PlatformConfig,
                                      &S3LateParams->StdHeader);
  if (CalledStatus > ReturnStatus) {
    ReturnStatus = CalledStatus;
  }

  CalledStatus = S3ScriptRestore (&S3LateParams->StdHeader);
  if (CalledStatus > ReturnStatus) {
    ReturnStatus = CalledStatus;
  }

  IDS_OPTION_HOOK (IDS_AFTER_S3_RESTORE, S3LateParams, &S3LateParams->StdHeader);
  AGESA_TESTPOINT (TpIfAmdS3LateRestoreExit, &S3LateParams->StdHeader);
  IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdS3LateRestore: End\n\n");
  IDS_HDT_CONSOLE_S3_EXIT (&S3LateParams->StdHeader);
  return  ReturnStatus;
}

/**
 * Main entry point for the AMD_INIT_ENV function.
 *
 * This entry point is responsible for copying the heap contents from the
 * temp RAM area to main memory.
 *
 * @param[in,out] EnvParams         Required input parameters for the AMD_INIT_ENV
 *                                  entry point.
 *
 * @return        Aggregated status across all internal AMD env calls invoked.
 *
 */
AGESA_STATUS
AmdInitEnv (
  IN OUT   AMD_ENV_PARAMS  *EnvParams
  )
{
  AGESA_STATUS  AgesaStatus;
  AGESA_STATUS  AmdInitEnvStatus;

  AGESA_TESTPOINT (TpIfAmdInitEnvEntry, &EnvParams->StdHeader);

  ASSERT (EnvParams != NULL);
  AmdInitEnvStatus = AGESA_SUCCESS;


  //Copy Temp Ram heap content to Main Ram
  AgesaStatus = CopyHeapToMainRamAtPost (&(EnvParams->StdHeader));
  if (AgesaStatus > AmdInitEnvStatus) {
    AmdInitEnvStatus = AgesaStatus;
  }
  EnvParams->StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
  EnvParams->StdHeader.HeapBasePtr = HeapGetBaseAddress (&EnvParams->StdHeader);
  // Any heap allocate/deallocate/locate buffer should be used after heap is rebuilt from here.
  // After persistent heaps are transferred and rebuilt, HeapLocateBuffer can start to be used in IDS hook.

  //Heap have been relocated, so Debug Print need be init again to get new address
  IDS_PERF_TIMESTAMP (TP_BEGINPROCAMDINITENV, &EnvParams->StdHeader);
  IDS_HDT_CONSOLE_INIT (&EnvParams->StdHeader);
  IDS_HDT_CONSOLE (MAIN_FLOW, "Heap transfer End\n");
  IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitEnv: Start\n\n");
  IDS_OPTION_HOOK (IDS_PLATFORMCFG_OVERRIDE, &EnvParams->PlatformConfig, &(EnvParams->StdHeader));
  IDS_OPTION_HOOK (IDS_BEFORE_PCI_INIT, EnvParams, &(EnvParams->StdHeader));

  AgesaStatus = S3ScriptInit (&EnvParams->StdHeader);
  if (AgesaStatus > AmdInitEnvStatus) {
    AmdInitEnvStatus = AgesaStatus;
  }

  IDS_PERF_TIMESTAMP (TP_BEGININITENV, &EnvParams->StdHeader);
  AgesaStatus = BldoptFchFunction.InitEnv (EnvParams);
  AmdInitEnvStatus = (AgesaStatus > AmdInitEnvStatus) ? AgesaStatus : AmdInitEnvStatus;
  IDS_PERF_TIMESTAMP (TP_ENDINITENV, &EnvParams->StdHeader);

  IDS_PERF_TIMESTAMP (TP_BEGINGNBINITATENV, &EnvParams->StdHeader);
  AgesaStatus = GnbInitAtEnv (EnvParams);
  if (AgesaStatus > AmdInitEnvStatus) {
    AmdInitEnvStatus = AgesaStatus;
  }
  IDS_PERF_TIMESTAMP (TP_ENDGNBINITATENV, &EnvParams->StdHeader);

  AGESA_TESTPOINT (TpIfAmdInitEnvExit, &EnvParams->StdHeader);
  IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitEnv: End\n");
  IDS_PERF_TIMESTAMP (TP_ENDPROCAMDINITENV, &EnvParams->StdHeader);
  IDS_HDT_CONSOLE_FLUSH_BUFFER (&EnvParams->StdHeader);
  return  AmdInitEnvStatus;
}

BOOLEAN
MemNDQSTiming3Nb (
  IN OUT   MEM_NB_BLOCK *NBPtr
  )
{
  MEM_TECH_BLOCK *TechPtr;

  TechPtr = NBPtr->TechPtr;
  if (TechPtr->NBPtr->MCTPtr->NodeMemSize) {
    AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeDQSTraining, &NBPtr->MemPtr->StdHeader);
    if (AgesaHookBeforeDQSTraining (0, TechPtr->NBPtr->MemPtr) == AGESA_SUCCESS) {
      // Right now we do not have anything to do if the callout is implemented
    }
    AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeDQSTraining, &NBPtr->MemPtr->StdHeader);
    //Execute Technology specific training features
    if (memTechTrainingFeatDDR3.EnterHardwareTraining (TechPtr)) {
      if (memTechTrainingFeatDDR3.SwWLTraining (TechPtr)) {
        MemFInitTableDrive (NBPtr, MTAfterSwWLTrn);
        if (memTechTrainingFeatDDR3.HwBasedWLTrainingPart1 (TechPtr)) {
          MemFInitTableDrive (NBPtr, MTAfterHwWLTrnP1);
          if (memTechTrainingFeatDDR3.HwBasedDQSReceiverEnableTrainingPart1 (TechPtr)) {
            MemFInitTableDrive (NBPtr, MTAfterHwRxEnTrnP1);
            // If target speed is higher than start-up speed, do frequency change and second pass of WL
            if (MemTHwWlPart2 (TechPtr)) {
              if (memTechTrainingFeatDDR3.TrainExitHwTrn (TechPtr)) {
                IDS_OPTION_HOOK (IDS_PHY_DLL_STANDBY_CNTRL, NBPtr, &(NBPtr->MemPtr->StdHeader));
                if (memTechTrainingFeatDDR3.NonOptimizedSWDQSRecEnTrainingPart1 (TechPtr)) {
                  if (memTechTrainingFeatDDR3.OptimizedSwDqsRecEnTrainingPart1 (TechPtr)) {
                    MemFInitTableDrive (NBPtr, MTAfterSwRxEnTrn);
                    if (memTechTrainingFeatDDR3.NonOptimizedSRdWrPosTraining (TechPtr)) {
                      if (memTechTrainingFeatDDR3.OptimizedSRdWrPosTraining (TechPtr)) {
                        MemFInitTableDrive (NBPtr, MTAfterDqsRwPosTrn);
                        do {
                          if (memTechTrainingFeatDDR3.MaxRdLatencyTraining (TechPtr)) {
                            MemFInitTableDrive (NBPtr, MTAfterMaxRdLatTrn);
                          }
                        } while (NBPtr->ChangeNbFrequency (NBPtr));
                      }
                    }
                  }
                }
              }
            }
          }
        }
      }
    }
    MemTMarkTrainFail (TechPtr);
  }
  return TRUE;
}

BOOLEAN
MemNInitMCTNb (
  IN OUT   MEM_NB_BLOCK *NBPtr
  )
{
  MEM_TECH_BLOCK *TechPtr;
  UINT8 Dct;
  BOOLEAN Flag;
  ID_INFO CallOutIdInfo;

  TechPtr = NBPtr->TechPtr;
  // Switch Tech functions for Nb
  NBPtr->TechBlockSwitch (NBPtr);
  // Start Memory controller initialization sequence
  Flag = FALSE;
  if (TechPtr->DimmPresence (TechPtr)) {
    AGESA_TESTPOINT (TpProcMemPlatformSpecificInit, &(NBPtr->MemPtr->StdHeader));
    if (NBPtr->MemNPlatformSpecificFormFactorInitNb (NBPtr)) {
      AGESA_TESTPOINT (TpProcMemSpdTiming, &(NBPtr->MemPtr->StdHeader));
      if (TechPtr->SpdCalcWidth (TechPtr)) {
        AGESA_TESTPOINT (TpProcMemSpeedTclConfig, &(NBPtr->MemPtr->StdHeader));
        if (TechPtr->SpdGetTargetSpeed (TechPtr)) {
          for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
            NBPtr->SwitchDCT (NBPtr, Dct);

            Flag |= MemNInitDCTNb (NBPtr);
          }

          if (Flag && !NBPtr->IsSupported[TwoStageDramInit] && (NBPtr->MCTPtr->ErrCode != AGESA_FATAL)) {
            MemFInitTableDrive (NBPtr, MTBeforeDInit);
            AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeDramInit, &(NBPtr->MemPtr->StdHeader));
            IDS_PERF_TIMESTAMP (TP_BEGINAGESAHOOKBEFOREDRAMINIT, &(NBPtr->MemPtr->StdHeader));
            CallOutIdInfo.IdField.SocketId = NBPtr->MCTPtr->SocketId;
            CallOutIdInfo.IdField.ModuleId = NBPtr->MCTPtr->DieId;
            IDS_HDT_CONSOLE (MEM_FLOW, "\nCalling out to Platform BIOS on Socket %d Module %d...\n", CallOutIdInfo.IdField.SocketId, CallOutIdInfo.IdField.ModuleId);
            AgesaHookBeforeDramInit ((UINTN) CallOutIdInfo.IdInformation, NBPtr->MemPtr);
            IDS_HDT_CONSOLE (MEM_FLOW, "\nVDDIO = 1.%dV\n", (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) ? 5 :
                                                  (NBPtr->RefPtr->DDR3Voltage == VOLT1_35) ? 35 :
                                                  (NBPtr->RefPtr->DDR3Voltage == VOLT1_25) ? 25 : 999);
            AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeDramInit, &(NBPtr->MemPtr->StdHeader));
            IDS_PERF_TIMESTAMP (TP_ENDAGESAHOOKBEFOREDRAMINIT, &(NBPtr->MemPtr->StdHeader));
            IDS_OPTION_HOOK (IDS_BEFORE_DRAM_INIT, NBPtr, &(NBPtr->MemPtr->StdHeader));
            NBPtr->StartupDCT (NBPtr);
          }
        }
      }
    }
  }
  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode != AGESA_FATAL);
}

/**
 *
 *   This function initializes the default values in the MEM_DATA_STRUCT
 *
 *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
 *
 *     @retval      None
 */
VOID
MemNInitDefaultsLN (
  IN OUT   MEM_DATA_STRUCT *MemPtr
  )
{
  UINT8 Socket;
  UINT8 Channel;
  MEM_PARAMETER_STRUCT *RefPtr;
  AGESA_TESTPOINT (TpProcMemBeforeMemDataInit, &(MemPtr->StdHeader));
  ASSERT (MemPtr != NULL);
  RefPtr = MemPtr->ParameterListPtr;

  // Memory Map/Mgt.
  // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB
  RefPtr->BottomIo = 0xE0;
  RefPtr->UmaMode = UserOptions.CfgUmaMode;
  RefPtr->UmaSize = UserOptions.CfgUmaSize;
  RefPtr->MemHoleRemapping = TRUE;
  RefPtr->LimitMemoryToBelow1Tb = UserOptions.CfgLimitMemoryToBelow1Tb;
  //


  // Dram Timing
  RefPtr->UserTimingMode = UserOptions.CfgTimingModeSelect;
  RefPtr->MemClockValue = UserOptions.CfgMemoryClockSelect;
  for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) {
    for (Channel = 0; Channel < MAX_CHANNELS_PER_SOCKET; Channel++) {
      MemPtr->SocketList[Socket].ChannelPtr[Channel] = NULL;
      MemPtr->SocketList[Socket].TimingsPtr[Channel] = NULL;
    }
  }

  // Memory Clear
  RefPtr->EnableMemClr = TRUE;

  // TableBasedAlterations
  RefPtr->TableBasedAlterations = NULL;

  // Platform config table
  RefPtr->PlatformMemoryConfiguration = DefaultPlatformMemoryConfiguration;

  // Memory Restore
  RefPtr->MemRestoreCtl = FALSE;
  RefPtr->SaveMemContextCtl = FALSE;
  AmdS3ParamsInitializer (&RefPtr->MemContext);

  // Dram Configuration
  RefPtr->EnableBankIntlv = UserOptions.CfgMemoryEnableBankInterleaving;
  RefPtr->EnableNodeIntlv = FALSE;
  RefPtr->EnableChannelIntlv = UserOptions.CfgMemoryChannelInterleaving;
  RefPtr->EnableBankSwizzle = UserOptions.CfgBankSwizzle;
  RefPtr->EnableParity = FALSE;
  RefPtr->EnableOnLineSpareCtl = FALSE;

  // Dram Power
  RefPtr->EnablePowerDown = UserOptions.CfgMemoryPowerDown;

  // ECC
  RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature;
}

/**
 *
 * MemMStandardTraining
 *
 * This function implements standard memory training whereby training functions
 * for all nodes are run by the BSP.
 *
 *
 *     @param[in,out]   *mmPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
 *
 *     @return          TRUE -  No fatal error occurs.
 *     @return          FALSE - Fatal error occurs.
 */
BOOLEAN
MemMStandardTraining (
  IN OUT   MEM_MAIN_DATA_BLOCK *mmPtr
  )
{
  UINT8 Die;
  //
  // If training is disabled, return success.
  //
  if (!UserOptions.CfgDqsTrainingControl) {
    return TRUE;
  }
  //
  // Run Northbridge-specific Standard Training feature for each die.
  //
  IDS_HDT_CONSOLE (MEM_STATUS, "\nStart serial training\n");
  for (Die = 0 ; Die < mmPtr->DieCount ; Die ++ ) {
    IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Die);
    AGESA_TESTPOINT (TpProcMemBeforeAnyTraining, &(mmPtr->MemPtr->StdHeader));
    mmPtr->NBPtr[Die].BeforeDqsTraining (&mmPtr->NBPtr[Die]);
    mmPtr->NBPtr[Die].Execute1dMaxRdLatTraining = TRUE;
    mmPtr->NBPtr[Die].FeatPtr->Training (&mmPtr->NBPtr[Die]);
    mmPtr->NBPtr[Die].TechPtr->TechnologySpecificHook[LrdimmSyncTrainedDlys] (mmPtr->NBPtr[Die].TechPtr, NULL);
    mmPtr->NBPtr[Die].AfterDqsTraining (&mmPtr->NBPtr[Die]);
    if (mmPtr->NBPtr[Die].MCTPtr->ErrCode == AGESA_FATAL) {
      break;
    }
  }
  return (BOOLEAN) (Die == mmPtr->DieCount);
}

/**
 * Update microcode patch in current processor for Family15h OR.
 *
 * This function acts as a wrapper for calling the LoadMicrocodePatch
 * routine at AmdInitEarly.
 *
 * This particualr version implements a workaround to a potential problem caused
 * when upgrading the microcode on Orochi B1 processors.
 *
 *  @param[in]   FamilyServices      The current Family Specific Services.
 *  @param[in]   EarlyParams         Service parameters.
 *  @param[in]   StdHeader           Config handle for library and services.
 *
 */
VOID
F15OrLoadMicrocodePatchAtEarly (
  IN       CPU_SPECIFIC_SERVICES  *FamilyServices,
  IN       AMD_CPU_EARLY_PARAMS   *EarlyParams,
  IN       AMD_CONFIG_PARAMS      *StdHeader
  )
{
  UINT64         MsrValue;
  UINT64         BuCfg2MsrValue;
  UINT64         CuCfgMsrValue;
  BOOLEAN        IsPatchLoaded;

  AGESA_TESTPOINT (TpProcCpuLoadUcode, StdHeader);

  if (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) {

    F15OrEarlySampleLoadMcuPatch.F15OrESAvoidNbCyclesStart (StdHeader, &BuCfg2MsrValue);

    // Erratum #655
    // Set MSR C001_1023[1] = 1b, prior to writing to MSR C001_1020
    LibAmdMsrRead (MSR_CU_CFG, &CuCfgMsrValue, StdHeader);
    MsrValue = CuCfgMsrValue | BIT1;
    LibAmdMsrWrite (MSR_CU_CFG, &MsrValue, StdHeader);

    IsPatchLoaded =  F15OrEarlySampleLoadMcuPatch.F15OrUpdateMcuPatchHook (StdHeader);

    // Erratum #655
    // Restore MSR C001_1023[1] = previous setting
    LibAmdMsrWrite (MSR_CU_CFG, &CuCfgMsrValue, StdHeader);

    F15OrEarlySampleLoadMcuPatch.F15OrESAvoidNbCyclesEnd (StdHeader, &BuCfg2MsrValue);
    F15OrEarlySampleLoadMcuPatch.F15OrESAfterPatchLoaded (StdHeader, IsPatchLoaded);
  }
}

/**
 * Update microcode patch in current processor for Family14h ON.
 *
 * This function acts as a wrapper for calling the LoadMicrocodePatch
 * routine at AmdInitEarly.
 *
 *  @param[in]   FamilyServices      The current Family Specific Services.
 *  @param[in]   EarlyParams         Service parameters.
 *  @param[in]   StdHeader           Config handle for library and services.
 *
 */
VOID
F14OnLoadMicrocodePatchAtEarly (
  IN       CPU_SPECIFIC_SERVICES  *FamilyServices,
  IN       AMD_CPU_EARLY_PARAMS   *EarlyParams,
  IN       AMD_CONFIG_PARAMS      *StdHeader
  )
{
  UINT64 MsrValue;

  AGESA_TESTPOINT (TpProcCpuLoadUcode, StdHeader);
  // To load a microcode patch while using the cache as general storage,
  // the following steps are followed:
  // 1. Program MSRC001_102B[L2AllocDcFlushVictim]=1.
  // 2. Load the microcode patch.
  // 3. Program MSRC001_102B[L2AllocDcFlushVictim]=0.
  LibAmdMsrRead (MSR_BU_CFG3, &MsrValue, StdHeader);
  MsrValue = MsrValue | BIT7;
  LibAmdMsrWrite (MSR_BU_CFG3, &MsrValue, StdHeader);

  LoadMicrocodePatch (StdHeader);

  LibAmdMsrRead (MSR_BU_CFG3, &MsrValue, StdHeader);
  MsrValue = MsrValue & ~((UINT64)BIT7);
  LibAmdMsrWrite (MSR_BU_CFG3, &MsrValue, StdHeader);
}

/**
 * Perform initialization services required at the Early Init POST time point.
 *
 * Execution Cache, HyperTransport, and AP Init advanced services are performed.
 *
 * @param[in]     EarlyParams  The interface struct for all early services
 *
 * @return        The most severe AGESA_STATUS returned by any called service.
 *
 */
AGESA_STATUS
AmdInitEarly (
  IN OUT   AMD_EARLY_PARAMS  *EarlyParams
  )
{
  AGESA_STATUS  CalledAgesaStatus;
  AGESA_STATUS  EarlyInitStatus;
  WARM_RESET_REQUEST Request;
  UINT8 PrevRequestBit;
  UINT8 PrevStateBits;

  IDS_PERF_TIMESTAMP (TP_BEGINPROCAMDINITEARLY, &EarlyParams->StdHeader);

  AGESA_TESTPOINT (TpIfAmdInitEarlyEntry, &EarlyParams->StdHeader);

  EarlyInitStatus = AGESA_SUCCESS;

  // Setup ROM execution cache
  IDS_HDT_CONSOLE (MAIN_FLOW, "AllocateExecutionCache: Start\n");
  CalledAgesaStatus = AllocateExecutionCache (&EarlyParams->StdHeader, &EarlyParams->CacheRegion[0]);
  IDS_HDT_CONSOLE (MAIN_FLOW, "AllocateExecutionCache: End\n");
  if (CalledAgesaStatus > EarlyInitStatus) {
    EarlyInitStatus = CalledAgesaStatus;
  }

  IDS_HDT_CONSOLE_DEBUG_CODE (
    {
      extern CHAR8 *BldOptDebugOutput[];

      UINT8 i;
      for (i = 0; BldOptDebugOutput[i] != NULL; i++) {
        IDS_HDT_CONSOLE (MAIN_FLOW, "\t%s\n", BldOptDebugOutput[i]);
      }
    }
  )