本文整理匯總了C++中BIT函數的典型用法代碼示例。如果您正苦於以下問題：C++ BIT函數的具體用法？C++ BIT怎麽用？C++ BIT使用的例子？那麽, 這裏精選的函數代碼示例或許可以為您提供幫助。
在下文中一共展示了BIT函數的15個代碼示例，這些例子默認根據受歡迎程度排序。您可以為喜歡或者感覺有用的代碼點讚，您的評價將有助於係統推薦出更棒的C++代碼示例。
示例1: hostap_master_start_xmit
/* hard_start_xmit function for master radio interface wifi#.
* AP processing (TX rate control, power save buffering, etc.).
* Use hardware TX function to send the frame. */
int hostap_master_start_xmit(struct sk_buff *skb, struct net_device *dev)
{
struct hostap_interface *iface;
local_info_t *local;
int ret = NETDEV_TX_BUSY;
u16 fc;
struct hostap_tx_data tx;
ap_tx_ret tx_ret;
struct hostap_skb_tx_data *meta;
int no_encrypt = 0;
struct ieee80211_hdr *hdr;
iface = netdev_priv(dev);
local = iface->local;
tx.skb = skb;
tx.sta_ptr = NULL;
meta = (struct hostap_skb_tx_data *) skb->cb;
if (meta->magic != HOSTAP_SKB_TX_DATA_MAGIC) {
printk(KERN_DEBUG "%s: invalid skb->cb magic (0x%08x, "
"expected 0x%08x)\n",
dev->name, meta->magic, HOSTAP_SKB_TX_DATA_MAGIC);
ret = 0;
iface->stats.tx_dropped++;
goto fail;
}
if (local->host_encrypt) {
/* Set crypt to default algorithm and key; will be replaced in
* AP code if STA has own alg/key */
tx.crypt = local->crypt_info.crypt[local->crypt_info.tx_keyidx];
tx.host_encrypt = 1;
} else {
tx.crypt = NULL;
tx.host_encrypt = 0;
}
if (skb->len < 24) {
printk(KERN_DEBUG "%s: hostap_master_start_xmit: short skb "
"(len=%d)\n", dev->name, skb->len);
ret = 0;
iface->stats.tx_dropped++;
goto fail;
}
/* FIX (?):
* Wi-Fi 802.11b test plan suggests that AP should ignore power save
* bit in authentication and (re)association frames and assume tha
* STA remains awake for the response. */
tx_ret = hostap_handle_sta_tx(local, &tx);
skb = tx.skb;
meta = (struct hostap_skb_tx_data *) skb->cb;
hdr = (struct ieee80211_hdr *) skb->data;
fc = le16_to_cpu(hdr->frame_control);
switch (tx_ret) {
case AP_TX_CONTINUE:
break;
case AP_TX_CONTINUE_NOT_AUTHORIZED:
if (local->ieee_802_1x &&
ieee80211_is_data(hdr->frame_control) &&
meta->ethertype != ETH_P_PAE &&
!(meta->flags & HOSTAP_TX_FLAGS_WDS)) {
printk(KERN_DEBUG "%s: dropped frame to unauthorized "
"port (IEEE 802.1X): ethertype=0x%04x\n",
dev->name, meta->ethertype);
hostap_dump_tx_80211(dev->name, skb);
ret = 0; /* drop packet */
iface->stats.tx_dropped++;
goto fail;
}
break;
case AP_TX_DROP:
ret = 0; /* drop packet */
iface->stats.tx_dropped++;
goto fail;
case AP_TX_RETRY:
goto fail;
case AP_TX_BUFFERED:
/* do not free skb here, it will be freed when the
* buffered frame is sent/timed out */
ret = 0;
goto tx_exit;
}
/* Request TX callback if protocol version is 2 in 802.11 header;
* this version 2 is a special case used between hostapd and kernel
* driver */
if (((fc & IEEE80211_FCTL_VERS) == BIT(1)) &&
local->ap && local->ap->tx_callback_idx && meta->tx_cb_idx == 0) {
meta->tx_cb_idx = local->ap->tx_callback_idx;
/* remove special version from the frame header */
fc &= ~IEEE80211_FCTL_VERS;
hdr->frame_control = cpu_to_le16(fc);
}
//.........這裏部分代碼省略.........
示例2: RCU_GPIOxRST
/*!
\brief reset the peripherals
\param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum
only one parameter can be selected which is shown as below:
\arg RCU_GPIOxRST (x=A,B,C,D,E): reset GPIO ports
\arg RCU_AFRST : reset alternate function clock
\arg RCU_USBFSRST: reset USBFS
\arg RCU_TIMERxRST (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13): reset TIMER
\arg RCU_WWDGTRST: reset WWDGT
\arg RCU_SPIxRST (x=0,1,2): reset SPI
\arg RCU_USARTxRST (x=0,1,2): reset USART
\arg RCU_UARTxRST (x=3,4): reset UART
\arg RCU_I2CxRST (x=0,1): reset I2C
\arg RCU_CANxRST (x=0,1): reset CAN
\arg RCU_PMURST: reset PMU
\arg RCU_DACRST: reset DAC
\arg RCU_ADCxRST (x=0,1): reset ADC
\arg RCU_CTCRST: reset CTC
\arg RCU_BKPIRST: reset BKPI
\param[out] none
\retval none
*/
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
{
RCU_REG_VAL(periph_reset) |= BIT(RCU_BIT_POS(periph_reset));
}示例3: rcu_interrupt_enable
/*!
\brief enable the stabilization interrupt
\param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum
only one parameter can be selected which is shown as below:
\arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable
\arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable
\arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable
\arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable
\arg RCU_INT_PLLSTB: PLL stabilization interrupt enable
\arg RCU_INT_PLL1STB: PLL1 stabilization interrupt enable
\arg RCU_INT_PLL2STB: PLL2 stabilization interrupt enable
\arg RCU_INT_IRC48MSTB: IRC48M stabilization interrupt enable
\param[out] none
\retval none
*/
void rcu_interrupt_enable(rcu_int_enum stab_int)
{
RCU_REG_VAL(stab_int) |= BIT(RCU_BIT_POS(stab_int));
}示例4: ipu_crtc_init
static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
struct ipu_client_platformdata *pdata, struct drm_device *drm)
{
struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
int dp = -EINVAL;
int ret;
int id;
ret = ipu_get_resources(ipu_crtc, pdata);
if (ret) {
dev_err(ipu_crtc->dev, "getting resources failed with %d.\n",
ret);
return ret;
}
ret = imx_drm_add_crtc(drm, &ipu_crtc->base, &ipu_crtc->imx_crtc,
&ipu_crtc_helper_funcs, ipu_crtc->dev->of_node);
if (ret) {
dev_err(ipu_crtc->dev, "adding crtc failed with %d.\n", ret);
goto err_put_resources;
}
if (pdata->dp >= 0)
dp = IPU_DP_FLOW_SYNC_BG;
id = imx_drm_crtc_id(ipu_crtc->imx_crtc);
ipu_crtc->plane[0] = ipu_plane_init(ipu_crtc->base.dev, ipu,
pdata->dma[0], dp, BIT(id), true);
ret = ipu_plane_get_resources(ipu_crtc->plane[0]);
if (ret) {
dev_err(ipu_crtc->dev, "getting plane 0 resources failed with %d.\n",
ret);
goto err_remove_crtc;
}
/* If this crtc is using the DP, add an overlay plane */
if (pdata->dp >= 0 && pdata->dma[1] > 0) {
ipu_crtc->plane[1] = ipu_plane_init(ipu_crtc->base.dev, ipu,
pdata->dma[1],
IPU_DP_FLOW_SYNC_FG,
BIT(id), false);
if (IS_ERR(ipu_crtc->plane[1]))
ipu_crtc->plane[1] = NULL;
}
ipu_crtc->irq = ipu_plane_irq(ipu_crtc->plane[0]);
ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0,
"imx_drm", ipu_crtc);
if (ret < 0) {
dev_err(ipu_crtc->dev, "irq request failed with %d.\n", ret);
goto err_put_plane_res;
}
return 0;
err_put_plane_res:
ipu_plane_put_resources(ipu_crtc->plane[0]);
err_remove_crtc:
imx_drm_remove_crtc(ipu_crtc->imx_crtc);
err_put_resources:
ipu_put_resources(ipu_crtc);
return ret;
}示例5: BIT
void luxor_55_10828_device::abcbus_cs(UINT8 data)
{
UINT8 address = 0x2c | BIT(m_s1->read(), 0);
m_cs = (data == address);
}示例6: ath_paprd_calibrate
void ath_paprd_calibrate(struct work_struct *work)
{
struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work);
struct ieee80211_hw *hw = sc->hw;
struct ath_hw *ah = sc->sc_ah;
struct ieee80211_hdr *hdr;
struct sk_buff *skb = NULL;
struct ath9k_hw_cal_data *caldata = ah->caldata;
struct ath_common *common = ath9k_hw_common(ah);
int ftype;
int chain_ok = 0;
int chain;
int len = 1800;
int ret;
if (!caldata || !caldata->paprd_packet_sent || caldata->paprd_done)
return;
ath9k_ps_wakeup(sc);
if (ar9003_paprd_init_table(ah) < 0)
goto fail_paprd;
skb = alloc_skb(len, GFP_KERNEL);
if (!skb)
goto fail_paprd;
skb_put(skb, len);
memset(skb->data, 0, len);
hdr = (struct ieee80211_hdr *)skb->data;
ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC;
hdr->frame_control = cpu_to_le16(ftype);
hdr->duration_id = cpu_to_le16(10);
memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
if (!(ah->txchainmask & BIT(chain)))
continue;
chain_ok = 0;
ar9003_paprd_setup_gain_table(ah, chain);
ath_dbg(common, CALIBRATE,
"Sending PAPRD training frame on chain %d\n", chain);
if (!ath_paprd_send_frame(sc, skb, chain))
goto fail_paprd;
if (!ar9003_paprd_is_done(ah)) {
ath_dbg(common, CALIBRATE,
"PAPRD not yet done on chain %d\n", chain);
break;
}
ret = ar9003_paprd_create_curve(ah, caldata, chain);
if (ret == -EINPROGRESS) {
ath_dbg(common, CALIBRATE,
"PAPRD curve on chain %d needs to be re-trained\n",
chain);
break;
} else if (ret) {
ath_dbg(common, CALIBRATE,
"PAPRD create curve failed on chain %d\n",
chain);
break;
}
chain_ok = 1;
}
kfree_skb(skb);
if (chain_ok) {
caldata->paprd_done = true;
ath_paprd_activate(sc);
}
fail_paprd:
ath9k_ps_restore(sc);
}示例7: if
//.........這裏部分代碼省略.........
}
else if (functionName->isEqualTo(kFakeSMCGetKeyValue)) {
result = kIOReturnBadArgument;
if (const char *name = (const char *)param1) {
result = kIOReturnError;
if (FakeSMCKey *key = getKey(name)) {
result = kIOReturnBadArgument;
if (param2 && param3) {
UInt8 *size = (UInt8*)param2;
const void **value = (const void **)param3;
*size = key->getSize();
*value = key->getValue();
result = kIOReturnSuccess;
}
}
}
}
else if (functionName->isEqualTo(kFakeSMCTakeVacantGPUIndex)) {
result = kIOReturnBadArgument;
KEYSLOCK;
if (SInt8 *index = (SInt8*)param1) {
for (UInt8 i = 0; i <= 0xf; i++) {
if (!bit_get(vacantGPUIndex, BIT(i))) {
bit_set(vacantGPUIndex, BIT(i));
*index = i;
result = kIOReturnSuccess;
break;
}
}
if (result != kIOReturnSuccess)
result = kIOReturnError;
}
KEYSUNLOCK;
}
else if (functionName->isEqualTo(kFakeSMCTakeGPUIndex)) {
result = kIOReturnBadArgument;
KEYSLOCK;
if (UInt8 *index = (UInt8*)param1) {
if (*index < 0xf && !bit_get(vacantGPUIndex, BIT(*index))) {
bit_set(vacantGPUIndex, BIT(*index));
result = kIOReturnSuccess;
}
if (result != kIOReturnSuccess)
result = kIOReturnError;
}
KEYSUNLOCK;
}
else if (functionName->isEqualTo(kFakeSMCReleaseGPUIndex)) {示例8: ISL29028_DEV_ATTR
#define ISL29028_DEV_ATTR(name) (&iio_dev_attr_##name.dev_attr.attr)
#define ISL29028_CONST_ATTR(name) (&iio_const_attr_##name.dev_attr.attr)
static struct attribute *isl29028_attributes[] = {
ISL29028_CONST_ATTR(in_proximity_sampling_frequency_available),
ISL29028_CONST_ATTR(in_illuminance_scale_available),
NULL,
};
static const struct attribute_group isl29108_group = {
.attrs = isl29028_attributes,
};
static const struct iio_chan_spec isl29028_channels[] = {
{
.type = IIO_LIGHT,
.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) |
BIT(IIO_CHAN_INFO_SCALE) |
BIT(IIO_CHAN_INFO_RAW),
}, {
.type = IIO_INTENSITY,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
}, {
.type = IIO_PROXIMITY,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
BIT(IIO_CHAN_INFO_SAMP_FREQ),
}
};
static const struct iio_info isl29028_info = {
.attrs = &isl29108_group,
.driver_module = THIS_MODULE,示例9: send_assoc_resp
static void send_assoc_resp(struct hostapd_data *hapd, struct sta_info *sta,
u16 status_code, int reassoc, const u8 *ies,
size_t ies_len)
{
int send_len;
u8 buf[sizeof(struct ieee80211_mgmt) + 1024];
struct ieee80211_mgmt *reply;
u8 *p;
os_memset(buf, 0, sizeof(buf));
reply = (struct ieee80211_mgmt *) buf;
reply->frame_control =
IEEE80211_FC(WLAN_FC_TYPE_MGMT,
(reassoc ? WLAN_FC_STYPE_REASSOC_RESP :
WLAN_FC_STYPE_ASSOC_RESP));
os_memcpy(reply->da, sta->addr, ETH_ALEN);
os_memcpy(reply->sa, hapd->own_addr, ETH_ALEN);
os_memcpy(reply->bssid, hapd->own_addr, ETH_ALEN);
send_len = IEEE80211_HDRLEN;
send_len += sizeof(reply->u.assoc_resp);
reply->u.assoc_resp.capab_info =
host_to_le16(hostapd_own_capab_info(hapd, sta, 0));
reply->u.assoc_resp.status_code = host_to_le16(status_code);
reply->u.assoc_resp.aid = host_to_le16((sta ? sta->aid : 0)
| BIT(14) | BIT(15));
/* Supported rates */
p = hostapd_eid_supp_rates(hapd, reply->u.assoc_resp.variable);
/* Extended supported rates */
p = hostapd_eid_ext_supp_rates(hapd, p);
#ifdef CONFIG_IEEE80211R
if (status_code == WLAN_STATUS_SUCCESS) {
/* IEEE 802.11r: Mobility Domain Information, Fast BSS
* Transition Information, RSN, [RIC Response] */
p = wpa_sm_write_assoc_resp_ies(sta->wpa_sm, p,
buf + sizeof(buf) - p,
sta->auth_alg, ies, ies_len);
}
#endif /* CONFIG_IEEE80211R */
#ifdef CONFIG_IEEE80211W
if (status_code == WLAN_STATUS_ASSOC_REJECTED_TEMPORARILY)
p = hostapd_eid_assoc_comeback_time(hapd, sta, p);
#endif /* CONFIG_IEEE80211W */
#ifdef CONFIG_IEEE80211N
p = hostapd_eid_ht_capabilities(hapd, p);
p = hostapd_eid_ht_operation(hapd, p);
#endif /* CONFIG_IEEE80211N */
if (sta->flags & WLAN_STA_WMM)
p = hostapd_eid_wmm(hapd, p);
#ifdef CONFIG_WPS
if (sta->flags & WLAN_STA_WPS) {
struct wpabuf *wps = wps_build_assoc_resp_ie();
if (wps) {
os_memcpy(p, wpabuf_head(wps), wpabuf_len(wps));
p += wpabuf_len(wps);
wpabuf_free(wps);
}
}
#endif /* CONFIG_WPS */
send_len += p - reply->u.assoc_resp.variable;
if (hapd->drv.send_mgmt_frame(hapd, reply, send_len) < 0)
wpa_printf(MSG_INFO, "Failed to send assoc resp: %s",
strerror(errno));
}示例10: BIT
int superpet_device::pet_diag_r()
{
return BIT(m_system, 3);
}示例11: BIT
/* NVM SW-Section offset (in words) definitions */
NVM_VERSION_EXT_NVM = 0,
RADIO_CFG_FAMILY_EXT_NVM = 0,
SKU_FAMILY_8000 = 2,
N_HW_ADDRS_FAMILY_8000 = 3,
/* NVM REGULATORY -Section offset (in words) definitions */
NVM_CHANNELS_EXTENDED = 0,
NVM_LAR_OFFSET_OLD = 0x4C7,
NVM_LAR_OFFSET = 0x507,
NVM_LAR_ENABLED = 0x7,
};
/* SKU Capabilities (actual values from NVM definition) */
enum nvm_sku_bits {
NVM_SKU_CAP_BAND_24GHZ = BIT(0),
NVM_SKU_CAP_BAND_52GHZ = BIT(1),
NVM_SKU_CAP_11N_ENABLE = BIT(2),
NVM_SKU_CAP_11AC_ENABLE = BIT(3),
NVM_SKU_CAP_MIMO_DISABLE = BIT(5),
};
/*
* These are the channel numbers in the order that they are stored in the NVM
*/
static const u16 iwl_nvm_channels[] = {
/* 2.4 GHz */
1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
/* 5 GHz */
36, 40, 44 , 48, 52, 56, 60, 64,
100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,示例12: switch
void superpet_device::pet_bd_w(address_space &space, offs_t offset, uint8_t data, int &sel)
{
switch (sel)
{
case pet_expansion_slot_device::SEL9:
if (!m_sel9_rom && is_ram_writable())
{
m_ram[((m_bank & 0x0f) << 12) | (offset & 0xfff)] = data;
}
break;
}
switch (offset)
{
case 0xefe0:
case 0xefe1:
case 0xefe2:
case 0xefe3:
m_dongle->write(space, offset & 0x03, data);
printf("6702 %u %02x\n", offset & 0x03, data);
break;
case 0xeff0:
case 0xeff1:
case 0xeff2:
case 0xeff3:
m_acia->write(space, offset & 0x03, data);
break;
case 0xeff8:
case 0xeff9:
if (BIT(m_bank, 7))
{
/*
bit description
0 SW2 CPU (0=6809, 1=6502)
1 SW1 RAM (0=read only, 1=read/write)
2
3 DIAG
4
5
6
7
*/
m_system = data;
update_cpu();
printf("SYSTEM %02x\n", data);
}
break;
case 0xeffc:
case 0xeffd:
/*
bit description
0 A0
1 A1
2 A2
3 SEL A
4 J1 pin 40
5 SEL B
6 J1 pin 39
7 BIT 7
*/
m_bank = data;
printf("BANK %02x\n", data);
break;
}
}示例13: return
inline bool superpet_device::is_ram_writable()
{
return (m_sw1 == 2) ? BIT(m_system, 1) : m_sw1;
}示例14: ath_pci_probe
static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
struct ath_softc *sc;
struct ieee80211_hw *hw;
u8 csz;
u32 val;
int ret = 0;
char hw_name[64];
if (pcim_enable_device(pdev))
return -EIO;
ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
if (ret) {
pr_err("32-bit DMA not available\n");
return ret;
}
ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
if (ret) {
pr_err("32-bit DMA consistent DMA enable failed\n");
return ret;
}
/*
* Cache line size is used to size and align various
* structures used to communicate with the hardware.
*/
pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
if (csz == 0) {
/*
* Linux 2.4.18 (at least) writes the cache line size
* register as a 16-bit wide register which is wrong.
* We must have this setup properly for rx buffer
* DMA to work so force a reasonable value here if it
* comes up zero.
*/
csz = L1_CACHE_BYTES / sizeof(u32);
pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
}
/*
* The default setting of latency timer yields poor results,
* set it to the value used by other systems. It may be worth
* tweaking this setting more.
*/
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
pci_set_master(pdev);
/*
* Disable the RETRY_TIMEOUT register (0x41) to keep
* PCI Tx retries from interfering with C3 CPU state.
*/
pci_read_config_dword(pdev, 0x40, &val);
if ((val & 0x0000ff00) != 0)
pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
ret = pcim_iomap_regions(pdev, BIT(0), "ath9k");
if (ret) {
dev_err(&pdev->dev, "PCI memory region reserve error\n");
return -ENODEV;
}
ath9k_fill_chanctx_ops();
hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
if (!hw) {
dev_err(&pdev->dev, "No memory for ieee80211_hw\n");
return -ENOMEM;
}
SET_IEEE80211_DEV(hw, &pdev->dev);
pci_set_drvdata(pdev, hw);
sc = hw->priv;
sc->hw = hw;
sc->dev = &pdev->dev;
sc->mem = pcim_iomap_table(pdev)[0];
sc->driver_data = id->driver_data;
ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc);
if (ret) {
dev_err(&pdev->dev, "request_irq failed\n");
goto err_irq;
}
sc->irq = pdev->irq;
ret = ath9k_init_device(id->device, sc, &ath_pci_bus_ops);
if (ret) {
dev_err(&pdev->dev, "Failed to initialize device\n");
goto err_init;
}
ath9k_hw_name(sc->sc_ah, hw_name, sizeof(hw_name));
wiphy_info(hw->wiphy, "%s mem=0x%lx, irq=%d\n",
hw_name, (unsigned long)sc->mem, pdev->irq);
return 0;
err_init:
//.........這裏部分代碼省略.........
示例15: tvout_Change_dis_size
void tvout_Change_dis_size(u8 factor, bool updateFlag)
{
static u8 u8pre_factor = 0;
u32 tmpLCDcon46 = 0;
u32 lcd_con_reg_save;
if(!updateFlag)
{
if(u8pre_factor != factor)
u8pre_factor = factor;
else
return;
}
switch(factor)
{
case 0:
lcd_con_reg_save = REG32(LCDCON0);
DIS_OSD1();
DIS_OSD2();
DIS_OSD3();
lcd_set_panel_colour(0,0,0);
#if(0 == LCD_MCU)
waittingLcdFrameEnd();
REG32(LCDCON0) &= ~(BIT(0)|BIT(6));
tmpLCDcon46 = REG32(LCDCON46);
tvout_Set_Dis_Offset(0,0,u32csi_Dma_Size_H);
while (tmpLCDcon46 == REG32(LCDCON46));
tvout_display_set(0,0,u32csi_Dma_Size_H,u32csi_Dma_Size_H,u32csi_Dma_Size_V,tvout_get_w(),tvout_get_h());
REG32(LCDCON0) = lcd_con_reg_save;
REG32(LCDCON0) |= (BIT(0)|BIT(6));
#else
REG32(LCDCON0) &= ~(BIT(6));
waittingLcdFrameEnd();
tmpLCDcon46 = REG32(LCDCON46);
tvout_Set_Dis_Offset(0,0,u32csi_Dma_Size_H);
while (tmpLCDcon46 == REG32(LCDCON46));
tvout_display_set(0,0,u32csi_Dma_Size_H,u32csi_Dma_Size_H,u32csi_Dma_Size_V,tvout_get_w(),tvout_get_h());
waittingLcdFrameEnd();
REG32(LCDCON0) = lcd_con_reg_save;
REG32(LCDCON0) |= (BIT(6));
#endif
break;
case 1:
lcd_con_reg_save = REG32(LCDCON0);
DIS_OSD1();
DIS_OSD2();
DIS_OSD3();
lcd_set_panel_colour(0,0,0);
#if(0 == LCD_MCU)
waittingLcdFrameEnd();
REG32(LCDCON0) &= ~(BIT(0)|BIT(6));
tmpLCDcon46 = REG32(LCDCON46);
tvout_Set_Dis_Offset(u32csi_Dma_Size_H/4,u32csi_Dma_Size_V/4,u32csi_Dma_Size_H);
while (tmpLCDcon46 == REG32(LCDCON46));
tvout_display_set(0,0,u32csi_Dma_Size_H,u32csi_Dma_Size_H/2,u32csi_Dma_Size_V/2,tvout_get_w(),tvout_get_h());
REG32(LCDCON0) = lcd_con_reg_save;
REG32(LCDCON0) |= (BIT(0)|BIT(6));
#else
REG32(LCDCON0) &= ~(BIT(6));
waittingLcdFrameEnd();
tmpLCDcon46 = REG32(LCDCON46);
tvout_Set_Dis_Offset(u32csi_Dma_Size_H/4,u32csi_Dma_Size_V/4,u32csi_Dma_Size_H);
while (tmpLCDcon46 == REG32(LCDCON46));
tvout_display_set(0,0,u32csi_Dma_Size_H,u32csi_Dma_Size_H/2,u32csi_Dma_Size_V/2,tvout_get_w(),tvout_get_h());
waittingLcdFrameEnd();
REG32(LCDCON0) = lcd_con_reg_save;
REG32(LCDCON0) |= (BIT(6));
#endif
break;
case 2:
lcd_con_reg_save = REG32(LCDCON0);
DIS_OSD1();
DIS_OSD2();
DIS_OSD3();
lcd_set_panel_colour(0,0,0);
#if(0 == LCD_MCU)
waittingLcdFrameEnd();
REG32(LCDCON0) &= ~(BIT(0)|BIT(6));
tmpLCDcon46 = REG32(LCDCON46);
tvout_Set_Dis_Offset(u32csi_Dma_Size_H*3/8,u32csi_Dma_Size_V*3/8,u32csi_Dma_Size_H);
while (tmpLCDcon46 == REG32(LCDCON46));
tvout_display_set(0,0,u32csi_Dma_Size_H,u32csi_Dma_Size_H/4,u32csi_Dma_Size_V/4,tvout_get_w(),tvout_get_h());
REG32(LCDCON0) = lcd_con_reg_save;
REG32(LCDCON0) |= (BIT(0)|BIT(6));
#else
REG32(LCDCON0) &= ~(BIT(6));
waittingLcdFrameEnd();
tmpLCDcon46 = REG32(LCDCON46);
tvout_Set_Dis_Offset(u32csi_Dma_Size_H*3/8,u32csi_Dma_Size_V*3/8,u32csi_Dma_Size_H);
while (tmpLCDcon46 == REG32(LCDCON46));
tvout_display_set(0,0,u32csi_Dma_Size_H,u32csi_Dma_Size_H/4,u32csi_Dma_Size_V/4,tvout_get_w(),tvout_get_h());
waittingLcdFrameEnd();
REG32(LCDCON0) = lcd_con_reg_save;
REG32(LCDCON0) |= (BIT(6));
#endif
break;
default:
break;
//.........這裏部分代碼省略.........